bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	Replace obsolete -mattr=n64 command line option with -target-abi=n64. No ↵	Vladimir Medic	2015-02-26	1	-2/+2
\| \| \| \| \| \|	functional changes. llvm-svn: 230628
*	[mips] MIPS-IV is broadly the same as MIPS64 so duplicate all -mcpu=mips64 ↵	Daniel Sanders	2014-04-14	1	-1/+2
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	tests with -mcpu=mips4 as a starting point Summary: Two exceptions to this: test/CodeGen/Mips/octeon.ll test/CodeGen/Mips/octeon_popcnt.ll these test extensions to MIPS64 One test is altered for MIPS-IV: test/CodeGen/Mips/mips64countleading.ll Tests dclo/dclz which were added in MIPS64. The MIPS-IV version tests that dclo/dclz are not emitted. Four tests fail and are not in this patch: test/CodeGen/Mips/abicalls.ll test/CodeGen/Mips/fcopysign-f32-f64.ll test/CodeGen/Mips/fcopysign.ll test/CodeGen/Mips/stack-alignment.ll Depends on D3343 Reviewers: matheusalmeida, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3344 llvm-svn: 206185
*	Pattern for f32 to i64 conversion.	Akira Hatanaka	2012-01-24	1	-0/+7
\| \| \| \|	llvm-svn: 148869
*	32-to-64-bit sext_inreg pattern.	Akira Hatanaka	2011-12-20	1	-0/+8
\| \| \| \|	llvm-svn: 147004
*	Remove definitions of double word shift plus 32 instructions. Assembler or	Akira Hatanaka	2011-12-19	1	-2/+2
\| \| \| \| \| \| \|	direct-object emitter should emit the appropriate shift instruction depending on the shift amount. llvm-svn: 146893
*	32 to 64-bit zext pattern.	Akira Hatanaka	2011-12-07	1	-0/+11
	llvm-svn: 146096