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* [mips] Sign extend i32 return values on MIPS64Stefan Maksimovic2018-07-261-8/+13
| | | | | | | | | | | | | Override getTypeForExtReturn so that functions returning an i32 typed value have it sign extended on MIPS64. Also provide patterns to get rid of unneeded sign extensions for arithmetic instructions which implicitly sign extend their results. Differential Revision: https://reviews.llvm.org/D48374 llvm-svn: 338019
* [mips][microMIPS] Extending size reduction pass with LWP and SWPZoran Jovanovic2018-06-131-2/+1
| | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The patch extends size reduction pass for MicroMIPS. It introduces reduction of two instructions into one instruction: Two SW instructions are transformed into one SWP instrucition. Two LW instructions are transformed into one LWP instrucition. Differential Revision: https://reviews.llvm.org/D39115 llvm-svn: 334595
* [mips] Remove codegen support from some 16 bit instructionsSimon Dardis2018-02-161-21/+15
| | | | | | | | | | | | These instructions conflict with their full length variants for the purposes of FastISel as they cannot be distingushed based on the number and type of operands and predicates. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D41285 llvm-svn: 325341
* [mips] Update some tests before posting a patch, NFC.Simon Dardis2017-12-141-371/+957
| | | | llvm-svn: 320715
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-46/+0
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* [DAG] combine assertsexts around a truncSanjay Patel2017-10-091-9/+15
| | | | | | | This was a suggested follow-up to: D37017 / https://reviews.llvm.org/rL313577 llvm-svn: 315206
* [mips] interAptiv based generic schedule modelSimon Dardis2016-09-011-5/+5
| | | | | | | | | | | This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
* [mips] Preparatory work for a generic schedulerSimon Dardis2016-08-241-6/+6
| | | | | | | | | | | | | Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-241-29/+16
| | | | llvm-svn: 273669
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [mips][microMIPS] Add CodeGen support for AND*, OR16, OR*, XOR*, NOT16 and ↵Zlatko Buljan2016-06-151-18/+591
| | | | | | | | NOR instructions Differential Revision: http://reviews.llvm.org/D16719 llvm-svn: 272764
* Revert r229675 - [mips] Avoid redundant sign extension of the result of ↵Vasileios Kalintiris2015-08-041-1/+5
| | | | | | | | | | | | | | | | binary bitwise instructions. It introduced two regressions on 64-bit big-endian targets running under N32 (MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4, and MultiSource/Applications/kimwitu++/kc) The issue is that on 64-bit targets comparisons such as BEQ compare the whole GPR64 but incorrectly tell the instruction selector that they operate on GPR32's. This leads to the elimination of i32->i64 extensions that are actually required by comparisons to work correctly. There's currently a patch under review that fixes this problem. llvm-svn: 243984
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-181-0/+8
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] Avoid redundant sign extension of the result of binary bitwise ↵Vasileios Kalintiris2015-02-181-5/+1
| | | | | | | | | | | | instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7581 llvm-svn: 229675
* [mips] Enable arithmetic and binary operations for the i128 data type.Vasileios Kalintiris2015-01-261-0/+20
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
* [mips] Add tests for bitwise binary and integer arithmetic operators.Vasileios Kalintiris2015-01-261-0/+75
Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7125 llvm-svn: 227087
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