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* [mips] Use mult/mflo pattern on 64-bit targets prior to MIPS64Simon Atanasyan2019-07-171-0/+3
| | | | | | The `MUL` instruction is available starting from the MIPS32/MIPS64 targets. llvm-svn: 366301
* [mips] Correct the predicates for a number of instructions.Simon Dardis2018-05-291-2/+2
| | | | | | | | | | Previously, their listed predicates were overridden at the scope level. Reviewers: atanasyan, abeserminji, smaksimovic Differential Revision: https://reviews.llvm.org/D46947 llvm-svn: 333405
* [mips] Removal of microMIPS64R6Aleksandar Beserminji2017-12-111-22/+0
| | | | | | | | | | | All files and parts of files related to microMIPS4R6 are removed. When target is microMIPS4R6, errors are printed. This is LLVM part of patch. Differential Revision: https://reviews.llvm.org/D35625 llvm-svn: 320350
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-10-201-1/+1
| | | | | | | This reverts commit r314507, because the original patch is causing test failures. llvm-svn: 316215
* [mips] Reordering callseq* nodes to be linearAleksandar Beserminji2017-09-291-1/+1
| | | | | | | | | | | | | Fix nested callseq* nodes by moving callseq_start after the arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear. Recommitting r314497. This version does not contain test which fails when compiler is not build in debug mode. Differential Revision: https://reviews.llvm.org/D37328 llvm-svn: 314507
* Revert "[mips] Reordering callseq* nodes to be linear"Aleksandar Beserminji2017-09-291-1/+1
| | | | | | | | | Added test relies on the compiler being built in debug mode, which may not be the case. This reverts commit r314497. llvm-svn: 314506
* [mips] Reordering callseq* nodes to be linearAleksandar Beserminji2017-09-291-1/+1
| | | | | | | | | | Fix nested callseq* nodes by moving callseq_start after the arguments calculation to temporary registers, so that callseq* nodes in resulting DAG are linear. Differential Revision: https://reviews.llvm.org/D37328 llvm-svn: 314497
* evert "[mips] Fix test mips64fpldst.ll with machine verifier enabled"Simon Dardis2017-06-071-1/+1
| | | | | | | This reverts commit r301394. It broke some internal buildbots, reverting while the issue is being investigated. llvm-svn: 304896
* [mips] Fix test mips64fpldst.ll with machine verifier enabledSagar Thakur2017-04-261-1/+1
| | | | | | | | | Removed micro mips register classes for gp initialization because gp initialization uses pure mips64 instruction. Even when compiling for micro mips, gp initialization can be done with pure mips64 instructions. Reviewed by Simon Dardis Differential: D32286 llvm-svn: 301394
* [DAG] optimize negation of boolSanjay Patel2016-10-191-15/+36
| | | | | | | | | | | | | | | | Use mask and negate for legalization of i1 source type with SIGN_EXTEND_INREG. With the mask, this should be no worse than 2 shifts. The mask can be eliminated in some cases, so that should be better than 2 shifts. This change exposed some missing folds related to negation: https://reviews.llvm.org/rL284239 https://reviews.llvm.org/rL284395 There may be others, so please let me know if you see any regressions. Differential Revision: https://reviews.llvm.org/D25485 llvm-svn: 284611
* [mips] interAptiv based generic schedule modelSimon Dardis2016-09-011-21/+21
| | | | | | | | | | | This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
* [mips] Preparatory work for a generic schedulerSimon Dardis2016-08-241-1/+1
| | | | | | | | | | | | | Extend instruction definitions from nearly all ISAs to include appropriate instruction itineraries. Change MIPS16s gp prologue generation to use real instructions instead of using a pseudo instruction. Reviewers: dsanders, vkalintiris Differential Review: https://reviews.llvm.org/D23548 llvm-svn: 279623
* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-241-30/+30
| | | | llvm-svn: 273669
* [mips] Don't derive the default ABI from the CPU in the backend.Daniel Sanders2016-06-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The backend has no reason to behave like a driver and should generally do as it's told (and error out if it can't) instead of trying to figure out what the API user meant. The default ABI is still derived from the arch component as a concession to backwards compatibility. API-users that previously passed an explicit CPU and a triple that was inconsistent with the CPU (e.g. mips-linux-gnu and mips64r2) may get a different ABI to what they got before. However, it's expected that there are no such users on the basis that CodeGen has been asserting that the triple is consistent with the selected ABI for several releases. API-users that were consistent or passed '' or 'generic' as the CPU will see no difference. Reviewers: sdardis, rafael Subscribers: rafael, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21466 llvm-svn: 273557
* [mips][microMIPS] Add CodeGen support for MUL* and DMUL* instructionsZlatko Buljan2016-05-061-0/+38
| | | | | | Differential Revision: http://reviews.llvm.org/D15744 llvm-svn: 268714
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-12/+12
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] MIPSR6 Instruction itinerariesVasileios Kalintiris2016-03-111-12/+12
| | | | | | | | | | | | | | Summary: Defines instruction itineraries for common MIPSR6 instructions. Patch by Simon Dardis. Reviewers: vkalintiris Subscribers: MatzeB, dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D17198 llvm-svn: 263229
* [mips] Add backend support for Mips32r[35] and Mips64r[35].Daniel Sanders2015-02-181-25/+33
| | | | | | | | | | | | | | | | | Summary: These ISA's didn't add any instructions so they are almost identical to Mips32r2 and Mips64r2. Even the ELF e_flags are the same, However the ISA revision in .MIPS.abiflags is 3 or 5 respectively instead of 2. Reviewers: vmedic Reviewed By: vmedic Subscribers: tomatabacu, llvm-commits, atanasyan Differential Revision: http://reviews.llvm.org/D7381 llvm-svn: 229695
* [mips] Enable arithmetic and binary operations for the i128 data type.Vasileios Kalintiris2015-01-261-16/+43
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for some operations that were missing from 128-bit integer types (add/sub/mul/sdiv/udiv... etc.). With these changes we can support the __int128_t and __uint128_t data types from C/C++. Depends on D7125 Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7143 llvm-svn: 227089
* [mips] Add preliminary support for the MIPS II target.Vasileios Kalintiris2014-11-111-0/+181
Summary: This patch enables code generation for the MIPS II target. Pre-Mips32 targets don't have the MUL instruction, so we add the correspondent pattern that uses the MULT/MFLO combination in order to retrieve the product. This is WIP as we don't support code generation for select nodes due to the lack of conditional-move instructions. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D6150 llvm-svn: 221686
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