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* [mips] Restrict tail call optimizationSimon Dardis2016-11-201-5/+5
| | | | | | | | | | | | The tail call optimization was being used without proper consideration of ABI requirements for saving and restoring the GP. This patch restricts tail call optimization to functions within the same translation unit. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D24763 llvm-svn: 287505
* [mips] Disable tail calls temporarilySimon Dardis2016-09-271-1/+1
| | | | | | | | | | Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
* [mips] Enable tail calls by defaultSimon Dardis2016-08-041-6/+6
| | | | | | | | | | | | | | | | | | Enable tail calls by default for (micro)MIPS(64). microMIPS is slightly more tricky than doing it for MIPS(R6) or microMIPSR6. microMIPS has two instruction encodings: 16bit and 32bit along with some restrictions on the size of the instruction that can fill the delay slot. For safe tail calls for microMIPS, the delay slot filler attempts to find a correct size instruction for the delay slot of TAILCALL pseudos. Reviewers: dsanders, vkalintris Subscribers: jfb, dsanders, sdardis, llvm-commits Differential Revision: https://reviews.llvm.org/D21138 llvm-svn: 277708
* [mips] Make Static a default relocation model for MIPS codegenPetar Jovanovic2016-04-111-1/+1
| | | | | | | | | | | | This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
* [mips] Make sure there is a chain edge dependency between loads that readAkira Hatanaka2013-11-091-7/+7
| | | | | | | | | formal arguments on the stack and stores created afterwards. We need this to ensure tail call optimized function calls do not write over the argument area of the stack before it is read out. llvm-svn: 194309
* [mips] Make sure loads from lazy-binding entries do not get CSE'd or hoisted outAkira Hatanaka2013-09-281-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | of loops. Previously, two consecutive calls to function "func" would result in the following sequence of instructions: 1. load $16, %got(func)($gp) // load address of lazy-binding stub. 2. move $25, $16 3. jalr $25 // jump to lazy-binding stub. 4. nop 5. move $25, $16 6. jalr $25 // jump to lazy-binding stub again. With this patch, the second call directly jumps to func's address, bypassing the lazy-binding resolution routine: 1. load $25, %got(func)($gp) // load address of lazy-binding stub. 2. jalr $25 // jump to lazy-binding stub. 3. nop 4. load $25, %got(func)($gp) // load resolved address of func. 5. jalr $25 // directly jump to func. llvm-svn: 191591
* [mips] Implement MipsTargetMachine::getInstrItineraryData().Akira Hatanaka2013-07-121-6/+6
| | | | llvm-svn: 186227
* [mips] Print move instructions.Akira Hatanaka2013-03-041-6/+6
| | | | | | "move $4, $5" is printed instead of "or $4, $5, $zero". llvm-svn: 176455
* [mips] Implement MipsRegisterInfo::getRegPressureLimit.Akira Hatanaka2013-01-221-1/+1
| | | | llvm-svn: 173197
* [mips] Use "or $r0, $r1, $zero" instead of "addu $r0, $zero, $r1" to copyAkira Hatanaka2012-12-201-6/+6
| | | | | | | | | | | physical register $r1 to $r0. GNU disassembler recognizes an "or" instruction as a "move", and this change makes the disassembled code easier to read. Original patch by Reed Kotler. llvm-svn: 170655
* Eliminate the stack slot used to save the global base register.Akira Hatanaka2012-07-251-2/+2
| | | | | | | | The long branch pass (fixed in r160601) no longer uses the global base register to compute addresses of branch destinations, so it is not necessary to reserve a slot on the stack. llvm-svn: 160703
* Fix test cases.Akira Hatanaka2012-06-141-2/+2
| | | | llvm-svn: 158435
* Change the default scheduler from Latency to ILP, since LatencyDan Gohman2011-10-241-4/+4
| | | | | | is going away. llvm-svn: 142810
* Fix test cases.Akira Hatanaka2011-09-091-1/+1
| | | | | | Generate code for Mips32r1 unless a Mips32r2 feature is tested. llvm-svn: 139433
* Change the chain input of nodes that load the address of a function. This changeAkira Hatanaka2011-06-241-2/+2
| | | | | | | | enables SelectionDAG::getLoad at MipsISelLowering.cpp:1914 to return a pre-existing node instead of redundantly create a new node every time it is called. llvm-svn: 133811
* Make $fp and $ra callee-saved registers and let PrologEpilogInserter handleAkira Hatanaka2011-05-201-2/+2
| | | | | | saving and restoring them. llvm-svn: 131745
* Fix bug in which nodes that write to argument registers do not get glued ↵Akira Hatanaka2011-05-201-5/+5
| | | | | | with the JALR node. Patch by Sasa Stankovic llvm-svn: 131714
* Align i64 arguments to 64 bit boundaries.Akira Hatanaka2011-05-191-0/+34
llvm-svn: 131668
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