bcm5719-llvm - Project Ortega BCM5719 LLVM

	Commit message (Collapse)	Author	Age	Files	Lines
*	[mips][dsp] Modify repl.ph to accept signed immediate values	Petar Jovanovic	2017-06-07	1	-1/+11
\| \| \| \| \| \| \| \| \| \| \| \|	Changed immediate type for repl.ph from uimm10 to simm10 as per the specs. Repl.qb still accepts uimm8. Both instructions now mimic the behaviour of GNU as. Patch by Stefan Maksimovic. Differential Revision: https://reviews.llvm.org/D33594 llvm-svn: 304918
*	[mips][dsp] Fix use without def on DSPCtrl registers read by rddsp intrinsic.	Daniel Sanders	2016-06-14	1	-1/+2
\| \| \| \| \| \| \| \| \| \|	Reviewers: sdardis Subscribers: dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21063 llvm-svn: 272647
*	[mips][mips64r6] madd/maddu/msub/msubu are not available on MIPS32r6/MIPS64r6	Daniel Sanders	2014-06-12	1	-1/+1
\| \| \| \| \| \| \| \| \| \| \| \| \| \| \| \|	Summary: This patch disables madd/maddu/msub/msubu in both the assembler and code generator. Depends on D3896 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3955 llvm-svn: 210762
*	[mips] Split the DSP control register and define one register for each field of	Akira Hatanaka	2013-05-03	1	-8/+3
\| \| \| \| \| \| \| \| \| \| \|	its fields. This removes false dependencies between DSP instructions which access different fields of the the control register. Implicit register operands are added to instructions RDDSP and WRDSP after instruction selection, depending on the value of the mask operand. llvm-svn: 181041
*	MIPS DSP: add operands to make sure instruction strings are being matched.	Akira Hatanaka	2012-09-28	1	-20/+20
\| \| \| \|	llvm-svn: 164849
*	MIPS DSP: other miscellaneous instructions.	Akira Hatanaka	2012-09-28	1	-0/+41
\| \| \| \|	llvm-svn: 164845
*	MIPS DSP: ABSQ_S.PH instruction sub-class.	Akira Hatanaka	2012-09-27	1	-0/+202
\| \| \| \|	llvm-svn: 164787
*	MIPS DSP: SHLL.QB instruction sub-class.	Akira Hatanaka	2012-09-27	1	-0/+180
\| \| \| \|	llvm-svn: 164786
*	Test case for r164755 and 164756.	Akira Hatanaka	2012-09-27	1	-0/+220
\| \| \| \|	llvm-svn: 164757
*	MIPS DSP: ADDU.QB instruction sub-class.	Akira Hatanaka	2012-09-27	1	-0/+239
\| \| \| \|	llvm-svn: 164754
*	MIPS DSP: Branch on Greater Than or Equal To Value 32 in DSPControl Pos ↵	Akira Hatanaka	2012-09-27	1	-0/+10
\| \| \| \| \| \|	Field instruction. llvm-svn: 164751
*	MIPS DSP: all the remaining instructions which read or write accumulators.	Akira Hatanaka	2012-09-27	1	-0/+239
\| \| \| \|	llvm-svn: 164750
*	MIPS DSP: add support for extract-word instructions.	Akira Hatanaka	2012-09-27	1	-0/+110
	llvm-svn: 164749