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* [mips] Use --check-prefixes where appropriate. NFC.Daniel Sanders2016-06-241-6/+6
| | | | llvm-svn: 273669
* [mips] Use MFHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-07-141-14/+20
| | | | | | | | | | | | | | FP64 moves Summary: This is similar to r210771 which did the same thing for MTHC1. Also corrected MTHC1_D32 and MTHC1_D64 which used AFGR64 and FGR64 on the wrong definitions. Differential Revision: http://reviews.llvm.org/D4483 llvm-svn: 212936
* [mips] Use MTHC1 when it is available (MIPS32r2 and later) for both FP32 and ↵Daniel Sanders2014-06-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | FP64 Summary: To make this work for both AFGR64 and FGR64 register sets, I've had to make the instruction definition consistent with the white lie (that it reads the lower 32-bits of the register) when they are generated by expandBuildPairF64(). Corrected the definition of hasMips32r2() and hasMips64r2() to include MIPS32r6 and MIPS64r6. Depends on D3956 Reviewers: jkolek, zoran.jovanovic, vmedic Reviewed By: vmedic Differential Revision: http://reviews.llvm.org/D3957 llvm-svn: 210771
* Add extra CHECK prefix to tests with explicit prefixNico Rieck2014-02-161-4/+4
| | | | | | | These tests mistakenly assume that CHECK is still available even if an explicit prefix is specified. llvm-svn: 201492
* [mips] Add support for mfhc1 and mthc1.Akira Hatanaka2013-08-201-6/+17
| | | | llvm-svn: 188848
* Make tests register allocation independent again.Jakob Stoklund Olesen2011-04-191-10/+6
| | | | llvm-svn: 129739
* Add pass that expands pseudo instructions into target instructions after ↵Akira Hatanaka2011-04-151-0/+27
register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions. llvm-svn: 129594
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