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* [MIPS GlobalISel] Select andi, ori and xoriPetar Avramovic2019-11-151-22/+84
| | | | | | | | | | | | | Introduce IntImmLeaf version of PatLeaf immZExt16 for 32-bit immediates. Change immZExt16 with imm32ZExt16 for andi, ori and xori. This keeps same behavior for SDAG and allows for GlobalISel selectImpl to select 'G_CONSTANT imm' + G_AND, G_OR, G_XOR into ANDi, ORi, XORi, respectively, when 32-bit imm satisfies imm32ZExt16 predicate: zero extending 16 low bits of imm is equal to imm. Large number of test changes comes from zero extending of small types which is transformed into 'and' with bitmask in legalizer. Differential Revision:https://reviews.llvm.org/D70185
* GlobalISel/TableGen: Handle setcc patternsMatt Arsenault2019-08-291-7/+3
| | | | | | | | | | | This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
* [MIPS GlobalISel] ClampScalar G_SHL, G_ASHR and G_LSHR Petar Avramovic2019-08-271-0/+140
| | | | | | | | ClampScalar G_SHL, G_ASHR and G_LSHR to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66533 llvm-svn: 370067
* [MIPS GlobalISel] ClampScalar G_AND G_OR and G_XORPetar Avramovic2018-12-181-7/+141
| | | | | | | | | | Add narrowScalar for G_AND and G_XOR. Legalize G_AND G_OR and G_XOR for types other then s32 with clampScalar on MIPS32. Differential Revision: https://reviews.llvm.org/D55362 llvm-svn: 349475
* [MIPS GlobalISel] Select bitwise instructionsPetar Jovanovic2018-08-211-0/+103
Select bitwise instructions for i32. Patch by Petar Avramovic. Differential Revision: https://reviews.llvm.org/D50183 llvm-svn: 340258
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