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* Migrate function attribute "no-frame-pointer-elim"="false" to ↵Fangrui Song2019-12-241-2/+2
| | | | "frame-pointer"="none" as cleanups after D56351
* Relax fast register allocator related test cases; NFCMatthias Braun2018-10-291-2/+2
| | | | | | | | | | | | | - Relex hard coded registers and stack frame sizes - Some test cleanups - Change phi-dbg.ll to match on mir output after phi elimination instead of going through the whole codegen pipeline. This is in preparation for https://reviews.llvm.org/D52010 I'm committing all the test changes upfront that work before and after independently. llvm-svn: 345532
* Re-commit: [mips][fastisel] Handle 0-4 arguments without SelectionDAG.Daniel Sanders2016-07-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. The previous commit had an uninitialized variable that caused the incoming argument region to have undefined size. This has been fixed. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 277136
* Revert r276982 and r276984: [mips][fastisel] Handle 0-4 arguments without ↵Daniel Sanders2016-07-281-2/+2
| | | | | | | | | SelectionDAG It seems that the stack offset in callabi.ll varies between machines. I'll look into it. llvm-svn: 276989
* [mips][fastisel] Handle 0-4 arguments without SelectionDAG.Daniel Sanders2016-07-281-2/+2
| | | | | | | | | | | | | | | | | | | Summary: Implements fastLowerArguments() to avoid the need to fall back on SelectionDAG for 0-4 argument functions that don't do tricky things like passing double in a pair of i32's. This allows us to move all except one test to -fast-isel-abort=3. The remaining one has function prototypes of the form 'i32 (i32, double, double)' which requires floats to be passed in GPR's. Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: https://reviews.llvm.org/D22680 llvm-svn: 276982
* [mips][FastISel] Remove hidden mips-fast-isel option.Vasileios Kalintiris2015-07-301-2/+2
| | | | | | | | | | | | | | | Summary: This hidden option would disable code generation through FastISel by default. It was removed from the available options and from the Fast-ISel tests that required it in order to run the tests. Reviewers: dsanders Subscribers: qcolombet, llvm-commits Differential Revision: http://reviews.llvm.org/D11610 llvm-svn: 243638
* [mips][FastISel] Apply only zero-extension to constants prior to their ↵Vasileios Kalintiris2015-07-301-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | materialization. Summary: Previously, we would sign-extend non-boolean negative constants and zero-extend otherwise. This was problematic for PHI instructions with negative values that had a type with bitwidth less than that of the register used for materialization. More specifically, ComputePHILiveOutRegInfo() assumes the constants present in a PHI node are zero extended in their container and afterwards deduces the known bits. For example, previously we would materialize an i16 -4 with the following instruction: addiu $r, $zero, -4 The register would end-up with the 32-bit 2's complement representation of -4. However, ComputePHILiveOutRegInfo() would generate a constant with the upper 16-bits set to zero. The SelectionDAG builder would use that information to generate an AssertZero node that would remove any subsequent trunc & zero_extend nodes. In theory, we should modify ComputePHILiveOutRegInfo() to consult target-specific hooks about the way they prefer to materialize the given constants. However, git-blame reports that this specific code has not been touched since 2011 and it seems to be working well for every target so far. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11592 llvm-svn: 243636
* Use sext in fast isel.Rafael Espindola2015-04-061-12/+13
| | | | | | | | | | | | | | | | | | Fast isel used to zero extends immediates to 64 bits. This normally goes unnoticed because the value is truncated to 32 bits for output. Two cases were it is noticed: * We fail to use smaller encodings. * If the original constant was smaller than i32. In the tests using i1 constants, codegen would change to use -1, which is fine (and matches what regular isel does) since only the lowest bit is then used. Instead, this patch then changes the ir to use i8 constants, which looks more like what clang produces. llvm-svn: 234249
* Add logical ops to Mips fast-iselReed Kotler2015-03-091-0/+605
Summary: Code is mostly copied from AArch64 port and modified where needed for Mips. This handles the "non" legal cases of logical ops. Legal cases are handled by tablegen patterns. Test Plan: Make check test logopm.ll All of test-suite passes at O0/O2 and mips32 r1/r2 with this new change. Reviewers: dsanders Reviewed By: dsanders Subscribers: echristo, llvm-commits, aemerson, rfuhler Differential Revision: http://reviews.llvm.org/D6599 llvm-svn: 231665
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