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* MachineVerifier: Add missing linebreakMatthias Braun2015-11-091-1/+2
| | | | | | | MachineInstr::print() with SkipOppers==true does not produce a linebreak, so we have to do that in MachineVerifier::report(). llvm-svn: 252551
* DI: Reverse direction of subprogram -> function edge.Peter Collingbourne2015-11-055-10/+10
| | | | | | | | | | | | | | | | | | | | | | | Previously, subprograms contained a metadata reference to the function they described. Because most clients need to get or set a subprogram for a given function rather than the other way around, this created unneeded inefficiency. For example, many passes needed to call the function llvm::makeSubprogramMap() to build a mapping from functions to subprograms, and the IR linker needed to fix up function references in a way that caused quadratic complexity in the IR linking phase of LTO. This change reverses the direction of the edge by storing the subprogram as function-level metadata and removing DISubprogram's function field. Since this is an IR change, a bitcode upgrade has been provided. Fixes PR23367. An upgrade script for textual IR for out-of-tree clients is attached to the PR. Differential Revision: http://reviews.llvm.org/D14265 llvm-svn: 252219
* Create a new interface addSuccessorWithoutWeight(MBB*) in MBB to add ↵Cong Hou2015-10-272-4/+4
| | | | | | | | | | | | | | successors when optimization is disabled. When optimization is disabled, edge weights that are stored in MBB won't be used so that we don't have to store them. Currently, this is done by adding successors with default weight 0, and if all successors have default weights, the weight list will be empty. But that the weight list is empty doesn't mean disabled optimization (as is stated several times in MachineBasicBlock.cpp): it may also mean all successors just have default weights. We should discourage using default weights when adding successors, because it is very easy for users to forget update the correct edge weights instead of using default ones (one exception is that the MBB only has one successor). In order to detect such usages, it is better to differentiate using default weights from the case when optimizations is disabled. In this patch, a new interface addSuccessorWithoutWeight(MBB*) is created for when optimization is disabled. In this case, MBB will try to maintain an empty weight list, but it cannot guarantee this as for many uses of addSuccessor() whether optimization is disabled or not is not checked. But it can guarantee that if optimization is enabled, then the weight list always has the same size of the successor list. Differential revision: http://reviews.llvm.org/D13963 llvm-svn: 251429
* [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.Daniel Sanders2015-10-152-2/+2
| | | | | | | | | | | | | | | | Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
* Fix PR 24724 - The implicit register verifier shouldn't assume certain operandAlex Lorenz2015-09-104-2/+49
| | | | | | | | | | order. The implicit register verifier in the MIR parser should only check if the instruction's default implicit operands are present in the instruction. It should not check the order in which they occur. llvm-svn: 247283
* Fix PR 24633 - Handle undef values when parsing standalone constants.Alex Lorenz2015-09-091-0/+16
| | | | llvm-svn: 247145
* DI: Require subprogram definitions to be distinctDuncan P. N. Exon Smith2015-08-287-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | As a follow-up to r246098, require `DISubprogram` definitions (`isDefinition: true`) to be 'distinct'. Specifically, add an assembler check, a verifier check, and bitcode upgrading logic to combat testcase bitrot after the `DIBuilder` change. While working on the testcases, I realized that test/Linker/subprogram-linkonce-weak-odr.ll isn't relevant anymore. Its purpose was to check for a corner case in PR22792 where two subprogram definitions match exactly and share the same metadata node. The new verifier check, requiring that subprogram definitions are 'distinct', precludes that possibility. I updated almost all the IR with the following script: git grep -l -E -e '= !DISubprogram\(.* isDefinition: true' | grep -v test/Bitcode | xargs sed -i '' -e 's/= \(!DISubprogram(.*, isDefinition: true\)/= distinct \1/' Likely some variant of would work for out-of-tree testcases. llvm-svn: 246327
* MIR Serialization: Serialize the pointer IR expression values in the machineAlex Lorenz2015-08-212-2/+27
| | | | | | memory operands. llvm-svn: 245745
* MIR Serialization: Use the global value syntax for global value memory operands.Alex Lorenz2015-08-203-10/+17
| | | | | | | | | | | This commit modifies the serialization syntax so that the global IR values in machine memory operands use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. The unnamed global IR values are handled by this commit as well, as the existing global value parsing method can parse the unnamed globals already. llvm-svn: 245527
* MIR Serialization: Change syntax for the call entry pseudo source values.Alex Lorenz2015-08-202-6/+47
| | | | | | | | | | | | The global IR values in machine memory operands should use the global value '@<name>' syntax instead of the current '%ir.<name>' syntax. However, the global value call entry pseudo source values use the global value syntax already. Therefore, the syntax for the call entry pseudo source values has to be changed so that the global values and call entry global value PSVs can be parsed without ambiguities. llvm-svn: 245526
* MIR Serialization: Serialize unnamed local IR values in memory operands.Alex Lorenz2015-08-191-0/+30
| | | | llvm-svn: 245521
* MIR Serialization: Serialize instruction's register ties.Alex Lorenz2015-08-196-0/+150
| | | | | | | | This commit serializes the machine instruction's register operand ties. The ties are printed out only when the instructon has register ties that are different from the ties that are specified in the instruction's description. llvm-svn: 245482
* MIR Serialization: Serialize defined registers that require 'def' register flag.Alex Lorenz2015-08-191-0/+29
| | | | | | | | | The defined registers are already serialized - they are represented by placing them before the '=' in a machine instruction. However, certain instructions like INLINEASM can have defined register operands after the '=', so this commit introduces the 'def' register flag for such operands. llvm-svn: 245480
* MIR Serialization: Serialize MMI's variable debug information.Alex Lorenz2015-08-193-0/+143
| | | | llvm-svn: 245396
* MIR Parser: Return true on error when parsing standalone registers.Alex Lorenz2015-08-181-0/+24
| | | | llvm-svn: 245384
* MIR Serialization: Serialize the operand's bit mask target flags.Alex Lorenz2015-08-183-0/+85
| | | | | | | | | This commit adds support for bit mask target flag serialization to the MIR printer and the MIR parser. It also adds support for the machine operand's target flag serialization to the AArch64 target. Reviewers: Duncan P. N. Exon Smith llvm-svn: 245383
* MIR Serialization: Serialize the frame information's stack protector index.Alex Lorenz2015-08-182-0/+146
| | | | llvm-svn: 245372
* MIR Parser: Implicit register verifier should accept unexpected implicitAlex Lorenz2015-08-181-0/+30
| | | | | | subregister operands. llvm-svn: 245315
* MIR Serialization: Serialize the local offsets for the stack objects.Alex Lorenz2015-08-171-0/+41
| | | | llvm-svn: 245249
* MIR Serialization: Serialize the memory operand's range metadata node.Alex Lorenz2015-08-171-0/+22
| | | | llvm-svn: 245247
* MIR Serialization: Serialize the memory operand's noalias metadata node.Alex Lorenz2015-08-171-1/+2
| | | | llvm-svn: 245246
* MIR Serialization: Serialize the memory operand's alias scope metadata node.Alex Lorenz2015-08-171-0/+33
| | | | llvm-svn: 245245
* MIR Serialization: Serialize the memory operand's TBAA metadata node.Alex Lorenz2015-08-172-0/+59
| | | | llvm-svn: 245244
* MIR Serialization: Serialize the '.cfi_same_value' CFI directive.Alex Lorenz2015-08-141-0/+80
| | | | llvm-svn: 245103
* MIR Serialization: Serialize the external symbol call entry pseudo sourceAlex Lorenz2015-08-141-0/+55
| | | | | | values. llvm-svn: 245098
* MIR Serialization: Serialize the global value call entry pseudo source values.Alex Lorenz2015-08-142-0/+49
| | | | llvm-svn: 245097
* MIR Serialization: Serialize the 'internal' register operand flag.Alex Lorenz2015-08-141-5/+5
| | | | llvm-svn: 245085
* MIR Serialization: Serialize the bundled machine instructions.Alex Lorenz2015-08-145-0/+177
| | | | llvm-svn: 245082
* MIR Serialization: Change MIR syntax - use custom syntax for MBBs.Alex Lorenz2015-08-13144-2281/+2111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit modifies the way the machine basic blocks are serialized - now the machine basic blocks are serialized using a custom syntax instead of relying on YAML primitives. Instead of using YAML mappings to represent the individual machine basic blocks in a machine function's body, the new syntax uses a single YAML block scalar which contains all of the machine basic blocks and instructions for that function. This is an example of a function's body that uses the old syntax: body: - id: 0 name: entry instructions: - '%eax = MOV32r0 implicit-def %eflags' - 'RETQ %eax' ... The same body is now written like this: body: | bb.0.entry: %eax = MOV32r0 implicit-def %eflags RETQ %eax ... This syntax change is motivated by the fact that the bundled machine instructions didn't map that well to the old syntax which was using a single YAML sequence to store all of the machine instructions in a block. The bundled machine instructions internally use flags like BundledPred and BundledSucc to determine the bundles, and serializing them as MI flags using the old syntax would have had a negative impact on the readability and the ease of editing for MIR files. The new syntax allows me to serialize the bundled machine instructions using a block construct without relying on the internal flags, for example: BUNDLE implicit-def dead %itstate, implicit-def %s1 ... { t2IT 1, 24, implicit-def %itstate %s1 = VMOVS killed %s0, 1, killed %cpsr, implicit killed %itstate } This commit also converts the MIR testcases to the new syntax. I developed a script that can convert from the old syntax to the new one. I will post the script on the llvm-commits mailing list in the thread for this commit. llvm-svn: 244982
* MIR Parser: Don't allow negative alignments for memory operands.Alex Lorenz2015-08-131-0/+32
| | | | llvm-svn: 244953
* MIR Parser: Allow the MI IR references to reference global values.Alex Lorenz2015-08-121-0/+21
| | | | | | | This commit fixes a bug where MI parser couldn't resolve the named IR references that referenced named global values. llvm-svn: 244817
* MIR Serialization: Serialize the fixed stack pseudo source values.Alex Lorenz2015-08-121-0/+41
| | | | llvm-svn: 244816
* MIR Serialization: Serialize the jump table pseudo source values.Alex Lorenz2015-08-121-0/+76
| | | | llvm-svn: 244813
* MIR Serialization: Serialize the GOT pseudo source values.Alex Lorenz2015-08-121-0/+23
| | | | llvm-svn: 244809
* MIR Serialization: Serialize the stack pseudo source values.Alex Lorenz2015-08-121-0/+35
| | | | llvm-svn: 244806
* MIR Serialization: Serialize the constant pool pseudo source values.Alex Lorenz2015-08-121-0/+26
| | | | llvm-svn: 244803
* MIR Serialization: Serialize UsedPhysRegMask from the machine register info.Alex Lorenz2015-08-111-0/+113
| | | | | | | | | | | | This commit serializes the UsedPhysRegMask register mask from the machine register information class. The mask is serialized as an inverted 'calleeSavedRegisters' mask to keep the output minimal. This commit also allows the MIR parser to infer this mask from the register mask operands if the machine function doesn't specify it. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244548
* MIR Parser: Report an error when a stack object is redefined.Alex Lorenz2015-08-101-0/+38
| | | | llvm-svn: 244536
* MIR Parser: Report an error when a fixed stack object is redefined.Alex Lorenz2015-08-101-0/+30
| | | | llvm-svn: 244534
* MIR Serialization: Serialize the liveout register mask machine operands.Alex Lorenz2015-08-101-0/+43
| | | | llvm-svn: 244529
* MIR Serialization: Serialize the base alignment for the machine memory operands.Alex Lorenz2015-08-073-0/+95
| | | | llvm-svn: 244357
* MIR Serialization: Serialize the offsets for the machine memory operands.Alex Lorenz2015-08-071-0/+31
| | | | llvm-svn: 244356
* MIR Serialization: Fix serialization of unnamed IR block references.Alex Lorenz2015-08-061-1/+22
| | | | | | | | The block address machine operands can reference IR blocks in other functions. This commit fixes a bug where the references to unnamed IR blocks in other functions weren't serialized correctly. llvm-svn: 244299
* MIR Parser: Report an error when parsing duplicate memory operand flags.Alex Lorenz2015-08-061-0/+29
| | | | llvm-svn: 244240
* MIR Serialization: Serialize the 'invariant' machine memory operand flag.Alex Lorenz2015-08-061-0/+23
| | | | llvm-svn: 244230
* MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.Alex Lorenz2015-08-061-0/+24
| | | | llvm-svn: 244228
* MIR Serialization: Initial serialization of the machine operand target flags.Alex Lorenz2015-08-064-0/+98
| | | | | | | | | | | | This commit implements the initial serialization of the machine operand target flags. It extends the 'TargetInstrInfo' class to add two new methods that help to provide text based serialization for the target flags. This commit can serialize only the X86 target flags, and the target flags for the other targets will be serialized in the follow-up commits. Reviewers: Duncan P. N. Exon Smith llvm-svn: 244185
* MIR Serialization: Serialize the machine operand's offset.Alex Lorenz2015-08-057-0/+182
| | | | | | | This commit serializes the offset for the following operands: target index, global address, external symbol, constant pool index, and block address. llvm-svn: 244157
* MIR Parser: Report an error when parsing large immediate operands.Alex Lorenz2015-08-051-0/+20
| | | | llvm-svn: 244100
* MIR Serialization: Serialize the typed immediate integer machine operands.Alex Lorenz2015-08-051-0/+35
| | | | llvm-svn: 244098
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