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* [MachineVerifier] Add check that tied physregs aren't different.Mikael Holmen2017-07-061-0/+22
| | | | | | | | | | | | | | | | Summary: Added MachineVerifier code to check register ties more thoroughly, especially so that physical registers that are tied are the same. This may help e.g. when creating MIR files. Original patch by Jesper Antonsson Reviewers: stoklund, sanjoy, qcolombet Reviewed By: qcolombet Subscribers: qcolombet, llvm-commits Differential Revision: https://reviews.llvm.org/D34394 llvm-svn: 307259
* AMDGPU: Add operand target flags serializationMatt Arsenault2017-07-021-0/+29
| | | | llvm-svn: 306995
* Remove redundant copy in recurrencesTaewook Oh2017-06-291-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If there is a chain of instructions formulating a recurrence, commuting operands can help removing a redundant copy. In the following example code, ``` BB#1: ; Loop Header %vreg0<def> = COPY %vreg13<kill>; GR32:%vreg0,%vreg13 ... BB#6: ; Loop Latch %vreg2<def> = COPY %vreg15<kill>; GR32:%vreg2,%vreg15 %vreg10<def,tied1> = ADD32rr %vreg1<kill,tied0>, %vreg0<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg10,%vreg1,%vreg0 %vreg3<def,tied1> = ADD32rr %vreg2<kill,tied0>, %vreg10<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg3,%vreg2,%vreg10 CMP32ri8 %vreg3, 10, %EFLAGS<imp-def>; GR32:%vreg3 %vreg13<def> = COPY %vreg3<kill>; GR32:%vreg13,%vreg3 JL_1 <BB#1>, %EFLAGS<imp-use,kill> ``` Existing two-address generation pass generates following code: ``` BB#1: %vreg0<def> = COPY %vreg13<kill>; GR32:%vreg0,%vreg13 ... BB#6: Predecessors according to CFG: BB#5 BB#4 %vreg2<def> = COPY %vreg15<kill>; GR32:%vreg2,%vreg15 %vreg10<def> = COPY %vreg1<kill>; GR32:%vreg10,%vreg1 %vreg10<def,tied1> = ADD32rr %vreg10<tied0>, %vreg0<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg10,%vreg0 %vreg3<def> = COPY %vreg10<kill>; GR32:%vreg3,%vreg10 %vreg3<def,tied1> = ADD32rr %vreg3<tied0>, %vreg2<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg3,%vreg2 CMP32ri8 %vreg3, 10, %EFLAGS<imp-def>; GR32:%vreg3 %vreg13<def> = COPY %vreg3<kill>; GR32:%vreg13,%vreg3 JL_1 <BB#1>, %EFLAGS<imp-use,kill> JMP_1 <BB#7> ``` This is suboptimal because the assembly code generated has a redundant copy at the end of #BB6 to feed %vreg13 to BB#1: ``` .LBB0_6: addl %esi, %edi addl %ebx, %edi cmpl $10, %edi movl %edi, %esi jl .LBB0_1 ``` This redundant copy can be elimiated by making instructions in the recurrence chain to compute the value "into" the register that actually holds the feedback value. In this example, this can be achieved by commuting %vreg0 and %vreg1 to compute %vreg10. With that change, code after two-address generation becomes ``` BB#1: %vreg0<def> = COPY %vreg13<kill>; GR32:%vreg0,%vreg13 ... BB#6: derived from LLVM BB %bb7 Predecessors according to CFG: BB#5 BB#4 %vreg2<def> = COPY %vreg15<kill>; GR32:%vreg2,%vreg15 %vreg10<def> = COPY %vreg0<kill>; GR32:%vreg10,%vreg0 %vreg10<def,tied1> = ADD32rr %vreg10<tied0>, %vreg1<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg10,%vreg1 %vreg3<def> = COPY %vreg10<kill>; GR32:%vreg3,%vreg10 %vreg3<def,tied1> = ADD32rr %vreg3<tied0>, %vreg2<kill>, %EFLAGS<imp-def,dead>; GR32:%vreg3,%vreg2 CMP32ri8 %vreg3, 10, %EFLAGS<imp-def>; GR32:%vreg3 %vreg13<def> = COPY %vreg3<kill>; GR32:%vreg13,%vreg3 JL_1 <BB#1>, %EFLAGS<imp-use,kill> JMP_1 <BB#7> ``` and the final assembly does not have redundant copy: ``` .LBB0_6: addl %edi, %eax addl %ebx, %eax cmpl $10, %eax jl .LBB0_1 ``` Reviewers: qcolombet, MatzeB, wmi Reviewed By: wmi Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D31821 llvm-svn: 306758
* llc: Add ability to parse mir from stdinMatthias Braun2017-06-061-0/+20
| | | | | | | | - Add -x <language> option to switch between IR and MIR inputs. - Change MIR parser to read from stdin when filename is '-'. - Add a simple mir roundtrip test. llvm-svn: 304825
* MIRPrinter: Avoid assert() when printing empty INLINEASM strings.Matthias Braun2017-06-061-0/+12
| | | | | | | | | | | CodeGen uses MO_ExternalSymbol to represent the inline assembly strings. Empty strings for symbol names appear to be invalid. For now just special case the output code to avoid hitting an `assert()` in `printLLVMNameWithoutPrefix()`. This fixes https://llvm.org/PR33317 llvm-svn: 304815
* Vivek Pandya2017-06-0613-33/+46
| | | | | | | | | | | | [Improve CodeGen Testing] This patch renables MIRPrinter print fields which have value equal to its default. If -simplify-mir option is passed then MIRPrinter will not print such fields. This change also required some lit test cases in CodeGen directory to be changed. Reviewed By: MatzeB Differential Revision: https://reviews.llvm.org/D32304 llvm-svn: 304779
* CodeGen: Refactor MIR parsingMatthias Braun2017-06-066-15/+22
| | | | | | | | | | | | When parsing .mir files immediately construct the MachineFunctions and put them into MachineModuleInfo. This allows us to get rid of the delayed construction (and delayed error reporting) through the MachineFunctionInitialzier interface. Differential Revision: https://reviews.llvm.org/D33809 llvm-svn: 304758
* [RABasic] Properly initialize the passQuentin Colombet2017-06-021-0/+1
| | | | | | | Use the initializeXXX method to initialize the RABasic pass in the pipeline. This enables us to take advantage of the .mir infrastructure. llvm-svn: 304602
* TargetMachine: Indicate whether machine verifier passes.Matthias Braun2017-05-311-2/+2
| | | | | | | | | | | | | This adds a callback to the LLVMTargetMachine that lets target indicate that they do not pass the machine verifier checks in all cases yet. This is intended to be a temporary measure while the targets are fixed allowing us to enable the machine verifier by default with EXPENSIVE_CHECKS enabled! Differential Revision: https://reviews.llvm.org/D33696 llvm-svn: 304320
* Revert "[IfConversion] Keep the CFG updated incrementally in IfConvertTriangle"Tobias Grosser2017-05-291-24/+0
| | | | | | | | | | | | | | | | | | The reverted change introdued assertions ala: "MachineBasicBlock::succ_iterator llvm::MachineBasicBlock::removeSuccessor(succ_iterator, bool): Assertion `I != Successors.end() && "Not a current successor!"' Mikael, the original committer, wrote me that he is working on a fix, but that it likely will take some time to get this resolved. As this bug is one of the last two issues that keep the AOSP buildbot from turning green, I revert the original commit r302876. I am looking forward to see this recommitted after the assertion has been resolved. llvm-svn: 304128
* Move machine-cse-physreg.mir to test/CodeGen/ThumbKrzysztof Parzyszek2017-05-241-35/+0
| | | | llvm-svn: 303778
* MachineCSE: Respect interblock physreg livenessMikael Holmen2017-05-241-0/+35
| | | | | | | | | | | | | | | | | | | | Summary: This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but if it is not marked dead, MachineCSE still wants to do its own check to see if it is trivially dead. This check for the trivial case assumed that physical registers cannot be live out of a block. Patch by Mattias Eriksson. Reviewers: qcolombet, jbhateja Reviewed By: qcolombet, jbhateja Subscribers: jbhateja, llvm-commits Differential Revision: https://reviews.llvm.org/D33408 llvm-svn: 303731
* [IfConversion] Keep the CFG updated incrementally in IfConvertTriangleMikael Holmen2017-05-121-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Instead of using RemoveExtraEdges (which uses analyzeBranch, which cannot always be trusted) at the end to fixup the CFG we keep the CFG updated as we go along and remove or add branches and merge blocks. This way we won't have any problems if the involved MBBs contain unanalyzable instructions. This fixes PR32721. In that case we had a triangle EBB | \ | | | TBB | / FBB where FBB didn't have any successors at all since it ended with an unconditional return. Then TBB and FBB were be merged into EBB, but EBB would still keep its successors, and the use of analyzeBranch and CorrectExtraCFGEdges wouldn't help to remove them since the return instruction is not analyzable (at least not on ARM). Reviewers: kparzysz, iteratee, MatzeB Reviewed By: iteratee Subscribers: aemerson, rengolin, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33037 llvm-svn: 302876
* [IfConversion] Add missing check in IfConversion/canFallThroughToMikael Holmen2017-05-101-0/+64
| | | | | | | | | | | | | | | | | Summary: When trying to figure out if MBB could fallthrough to ToMBB (possibly by falling through a bunch of other MBBs) we didn't actually check if there was fallthrough between the last two blocks in the chain. Reviewers: kparzysz, iteratee, MatzeB Reviewed By: kparzysz, iteratee Subscribers: javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D32996 llvm-svn: 302650
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* Add missing target triple to testMatthias Braun2017-05-051-1/+1
| | | | llvm-svn: 302301
* MIParser/MIRPrinter: Compute block successors if not explicitely specifiedMatthias Braun2017-05-054-29/+79
| | | | | | | | | | | | | | | | | - MIParser: If the successor list is not specified successors will be added based on basic block operands in the block and possible fallthrough. - MIRPrinter: Adds a new `simplify-mir` option, with that option set: Skip printing of block successor lists in cases where the parser is guaranteed to reconstruct it. This means we still print the list if some successor cannot be determined (happens for example for jump tables), if the successor order changes or branch probabilities being unequal. Differential Revision: https://reviews.llvm.org/D31262 llvm-svn: 302289
* MachineFrameInfo: Track whether MaxCallFrameSize is computed yet; NFCMatthias Braun2017-05-011-1/+0
| | | | | | | | | | This tracks whether MaxCallFrameSize is computed yet. Ideally we would assert and fail when the value is queried before it is computed, however this fails various targets that need to be fixed first. Differential Revision: https://reviews.llvm.org/D32570 llvm-svn: 301851
* MIR: Allow parsing of empty machine functionsJustin Bogner2017-04-118-41/+17
| | | | | | | | | | | | If you run llc -stop-after=codegenprepare and feed the resulting MIR to llc -start-after=codegenprepare, you'll have an empty machine function since we haven't run any isel yet. Of course, this only works if the MIRParser believes you that this is okay. This is essentially a revert of r241862 with a fix for the problem it was papering over. llvm-svn: 299975
* AMDGPU: Remove legacy bfe intrinsicsMatt Arsenault2017-04-031-2/+2
| | | | llvm-svn: 299372
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-215-14/+14
| | | | | | | | | | | | Currently the default C calling convention functions are treated the same as compute kernels. Make this explicit so the default calling convention can be changed to a non-kernel. Converted with perl -pi -e 's/define void/define amdgpu_kernel void/' on the relevant test directories (and undoing in one place that actually wanted a non-kernel). llvm-svn: 298444
* [MIR] Test assumes x64 windows calling convention upon printing/parsing MIR ↵Oren Ben Simhon2017-03-191-2/+2
| | | | | | output/input. llvm-svn: 298212
* [MIR] Add triple to test that assumes it runs on windows.Benjamin Kramer2017-03-191-1/+1
| | | | llvm-svn: 298211
* Moving the test to x86 because other architectures do not suport regcall ↵Oren Ben Simhon2017-03-191-0/+0
| | | | | | calling convention. llvm-svn: 298209
* [MIR] Support Customed Register Mask and CSRsOren Ben Simhon2017-03-192-109/+30
| | | | | | | | | | | | | The MIR printer dumps a string that describe the register mask of a function. A static predefined list of register masks matches a static list of strings. However when the register mask is not from the static predefined list, there is no descriptor string and the printer fails. This patch adds support to custom register mask printing and dumping. Also the list of callee saved registers (describing the registers that must be preserved for the caller) might be dynamic. As such this data needs to be dumped and parsed back to the Machine Register Info. Differential Revision: https://reviews.llvm.org/D30971 llvm-svn: 298207
* MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun2017-02-224-4/+4
| | | | | | | llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. llvm-svn: 295859
* AMDGPU: Remove dead declarations from MIR testsMatt Arsenault2017-02-213-48/+5
| | | | llvm-svn: 295755
* MIR: parse & print the atomic parts of a MachineMemOperand.Tim Northover2017-02-132-1/+31
| | | | | | We're going to need them very soon for GlobalISel. llvm-svn: 294992
* [MIRParser] Allow generic register specification on operand.Ahmed Bougacha2017-01-201-0/+3
| | | | | | | | This completes r292321 by adding support for generic registers, e.g.: %2:_(s32) = G_ADD %0, %1 llvm-svn: 292550
* MIRParser: Allow regclass specification on operandMatthias Braun2017-01-184-0/+71
| | | | | | | | | | | You can now define the register class of a virtual register on the operand itself avoiding the need to use a "registers:" block. Example: "%0:gr64 = COPY %rax" Differential Revision: https://reviews.llvm.org/D22398 llvm-svn: 292321
* [AArch64] Fold some filled/spilled subreg COPYsGeoff Berry2017-01-051-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Extend AArch64 foldMemoryOperandImpl() to handle folding spills of subreg COPYs with read-undef defs like: %vreg0:sub_32<def,read-undef> = COPY %WZR; GPR64:%vreg0 by widening the spilled physical source reg and generating: STRXui %XZR <fi#0> as well as folding fills of similar COPYs like: %vreg0:sub_32<def,read-undef> = COPY %vreg1; GPR64:%vreg0, GPR32:%vreg1 by generating: %vreg0:sub_32<def,read-undef> = LDRWui <fi#0> Reviewers: MatzeB, qcolombet Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D27425 llvm-svn: 291180
* CodeGen: Assert that liveness is up to date when reading block live-ins.Matthias Braun2017-01-052-4/+8
| | | | | | | | | | | | | | | | | Add an assert that checks whether liveins are up to date before they are used. - Do not print liveins into .mir files anymore in situations where they are out of date anyway. - The assert in the RegisterScavenger is superseded by the new one in livein_begin(). - Skip parts of the liveness updating logic in IfConversion.cpp when liveness isn't tracked anymore (just enough to avoid hitting the new assert()). Differential Revision: https://reviews.llvm.org/D27562 llvm-svn: 291169
* [GlobalISel] More fix for the size vs. type typo. NFC.Quentin Colombet2016-12-222-2/+2
| | | | | | I missed those in my previous commit (r290378). llvm-svn: 290387
* [MIRParser] Fix a typo in comment and error message.Quentin Colombet2016-12-221-2/+2
| | | | | | We have long switched from size to type. llvm-svn: 290378
* [MIRParser] Non-generic virtual register may have a type.Quentin Colombet2016-12-221-14/+0
| | | | | | | | When generic virtual registers get constrained, because of a use on a target specific operation for instance, we end up with regular virtual registers with a type and that's perfectly fine. llvm-svn: 290376
* Move test to correct directoryMatthias Braun2016-12-171-157/+0
| | | | | | See also test/CodeGen/MIR/README llvm-svn: 290032
* AMDGPU: Fix handling of 16-bit immediatesMatt Arsenault2016-12-101-0/+709
| | | | | | | | | | | | | | | | | | Since 32-bit instructions with 32-bit input immediate behavior are used to materialize 16-bit constants in 32-bit registers for 16-bit instructions, determining the legality based on the size is incorrect. Change operands to have the size specified in the type. Also adds a workaround for a disassembler bug that produces an immediate MCOperand for an operand that is supposed to be OPERAND_REGISTER. The assembler appears to accept out of bounds immediates and truncates them, but this seems to be an issue for 32-bit already. llvm-svn: 289306
* Add README describing the intention of test/CodeGen/MIRMatthias Braun2016-12-091-0/+7
| | | | llvm-svn: 289265
* Move .mir tests to appropriate directoriesMatthias Braun2016-12-0923-3379/+0
| | | | | | | | | | | test/CodeGen/MIR should contain tests that intent to test the MIR printing or parsing. Tests that test something else should be in test/CodeGen/TargetName even when they are written in .mir. As a rule of thumb, only tests using "llc -run-pass none" should be in test/CodeGen/MIR. llvm-svn: 289254
* AMDGPU: Refactor exp instructionsMatt Arsenault2016-12-052-1/+64
| | | | | | | | | | | | | | | Structure the definitions a bit more like the other classes. The main change here is to split EXP with the done bit set to a separate opcode, so we can set mayLoad = 1 so that it won't be reordered before the other exp stores, since this has the special constraint that if the done bit is set then this should be the last exp in she shader. Previously all exp instructions were inferred to have unmodeled side effects. llvm-svn: 288695
* AMDGPU: Move mir tests into mir test directoryMatt Arsenault2016-11-305-0/+647
| | | | llvm-svn: 288262
* AMDGPU/SI: Add back reverted SGPR spilling code, but disable itMarek Olsak2016-11-252-4/+177
| | | | | | suggested as a better solution by Matt llvm-svn: 287942
* Revert "AMDGPU: Implement SGPR spilling with scalar stores"Marek Olsak2016-11-251-173/+0
| | | | | | This reverts commit 4404d0d6e354e80dd7f8f0a0e12d8ad809cf007e. llvm-svn: 287936
* Revert "AMDGPU: Make m0 unallocatable"Marek Olsak2016-11-251-4/+4
| | | | | | This reverts commit 124ad83dae04514f943902446520c859adee0e96. llvm-svn: 287932
* AMDGPU: Make m0 unallocatableMatt Arsenault2016-11-241-4/+4
| | | | | | | | | | | m0 may need to be written for spill code, so we don't want general code uses relying on the value stored in it. This introduces a few code quality regressions where copies from m0 are not coalesced into copies of a copy of m0. llvm-svn: 287841
* [AArch64LoadStoreOptimizer] Don't treat write to XZR/WZR as a clobber.Geoff Berry2016-11-211-0/+27
| | | | | | | | | | | | | | | Summary: When searching for load/store instructions to pair/merge don't treat writes to WZR/XZR as clobbers since they don't change the value read from WZR/XZR (which is always 0). Reviewers: mcrosier, junbuml, jmolloy, t.p.northover Subscribers: aemerson, llvm-commits, rengolin Differential Revision: https://reviews.llvm.org/D26921 llvm-svn: 287592
* [MIRPrinter] XFAIL test for powerpcGeoff Berry2016-11-181-0/+2
| | | | | | | This test introduced in r287368 is failing on powerpc for reasons unrelated to branch probabilities. See PR31062. llvm-svn: 287375
* [MIRPrinter] Print raw branch probabilities as expected by MIRParserGeoff Berry2016-11-184-5/+31
| | | | | | | | | | | | Fixes PR28751. Reviewers: MatzeB, qcolombet Subscribers: mcrosier, llvm-commits Differential Revision: https://reviews.llvm.org/D26775 llvm-svn: 287368
* MIRParser: Add support for parsing vreg reg alloc hintsTom Stellard2016-11-151-2/+3
| | | | | | | | | | Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26573 llvm-svn: 286911
* RegAllocGreedy: Properly initialize this pass, so that -run-pass will workTom Stellard2016-11-141-0/+11
| | | | | | | | | | Reviewers: qcolombet, MatzeB Subscribers: wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D26572 llvm-svn: 286895
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