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* [llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.Puyan Lotfi2020-01-131-0/+23
* Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"...Fangrui Song2019-12-2416-16/+16
* Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" a...Fangrui Song2019-12-241-1/+1
* [llvm][MIRVRegNamerUtil] Adding hashing against MachineInstr flags.Puyan Lotfi2019-12-101-0/+37
* [llvm] Fixing MIRVRegNamerUtils to properly handle 2+ MachineBasicBlocks.Puyan Lotfi2019-12-041-0/+61
* [MIR] Add MIR parsing for heap alloc site instruction markersAmy Huang2019-11-051-0/+42
* [X86] Model MXCSR for all SSE instructionsCraig Topper2019-10-303-44/+44
* [BranchFolding] skip debug instr to avoid code changeJeremy Morse2019-10-291-0/+109
* Print quoted backslashes in LLVM IR as \\ instead of \5CReid Kleckner2019-10-101-1/+1
* Add a missing space in a MIR parser error messageDavid Stenberg2019-09-201-1/+1
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet2019-09-116-9/+9
* [DebugInfo] MCP: collect and update DBG_VALUEs encountered in local blockJeremy Morse2019-08-141-0/+7
* [MachineFunction] Base support for call site info trackingDjordje Todorovic2019-06-274-0/+92
* [X86] Introduce new MOVSSrm/MOVSDrm opcodes that use VR128 register class.Craig Topper2019-06-181-3/+3
* Describe stack-id as an enumSander de Smalen2019-06-177-17/+17
* [llvm-readobj] Change -long-option to --long-option in tests. NFCFangrui Song2019-05-011-1/+1
* [X86] Merge the different Jcc instructions for each condition code into singl...Craig Topper2019-04-0531-63/+63
* [X86] Add FPCW as an implicit use on floating point load instructions.Craig Topper2019-02-081-1/+1
* [X86] Add FPCW as a register and start using it as an implicit use on floatin...Craig Topper2019-02-081-2/+2
* MIR: Reject non-power-of-4 alignments in MMO parsingMatt Arsenault2019-01-301-0/+12
* [mir] Serialize DILocation inline when not possible to use a metadata referenceDaniel Sanders2018-12-131-0/+41
* [CodeGen] Fix bugs in BranchFolderPass when debug labels are generated.Hsiangkai Wang2018-11-301-0/+397
* Add 'REQUIRES: default_triple' to test/CodeGen/MIR/X86/zero-probability.mirDaniel Sanders2018-11-071-0/+1
* [codeview] Let the X86 backend tell us the VFRAME offset adjustmentReid Kleckner2018-11-031-2/+2
* MachineOperand/MIParser: Do not print debug-use flag, infer itMatthias Braun2018-10-303-6/+10
* [MIR] Simplify and move MIR testFrancis Visoiu Mistrih2018-10-261-0/+13
* [codeview] Emit S_FRAMEPROC and use S_DEFRANGE_FRAMEPOINTER_RELReid Kleckner2018-10-011-16/+15
* MIRParser: Check that instructions only reference DILocation metadataMatthias Braun2018-10-011-0/+15
* [DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.Carlos Alberto Enciso2018-10-011-0/+105
* add IR flags to MIMichael Berg2018-09-111-5/+6
* [NFC] - in preparation for adding nsw, nuw and exact as flags to MIMichael Berg2018-09-061-0/+19
* Consistently use MemoryLocation::UnknownSize to indicate unknown access sizeKrzysztof Parzyszek2018-08-203-2/+53
* [x86/MIR] Implement support for pre- and post-instruction symbols, asChandler Carruth2018-08-161-0/+82
* [DebugInfo][X86] Add start-after flags to MIR testsFrancis Visoiu Mistrih2018-07-121-1/+1
* [DebugInfo] Make sure all DBG_VALUEs' reguse operands have IsDebug propertyMikael Holmen2018-06-211-2/+2
* [MIRParser] Update a diagnostic message to use the correct register sigil. NFCMatt Davis2018-06-193-3/+3
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-096-7/+7
* MachineInst support mapping SDNode fast math flags for support in Back End co...Michael Berg2018-05-031-0/+36
* [MIR] Add support for debug metadata for fixed stack objectsFrancis Visoiu Mistrih2018-04-258-15/+62
* [MIR] Allow frame-setup and frame-destroy on the same instructionFrancis Visoiu Mistrih2018-03-131-0/+4
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-31130-1102/+1102
* Add triples or specify REQUIRES: default_triple to some testsJustin Bogner2018-01-273-3/+3
* [x86] Mostly reautogenerate a bunch of tests that affect D37775. NFCAlexander Ivchenko2018-01-231-3/+3
* Move tests to the correct placeMatthias Braun2018-01-195-317/+0
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-1011-27/+27
* [MIR] Add support for the frame-destroy MachineInstr flagFrancis Visoiu Mistrih2018-01-091-1/+2
* [YAML] Add support for non-printable charactersFrancis Visoiu Mistrih2017-12-181-0/+6
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-151-1/+1
* Ignore metainstructions during the shrink wrap analysisAdrian Prantl2017-12-131-0/+182
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-0/+16
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