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* [PowerPC][NFC] Move codegen tests to PowerPC from MIR/PowerPCJinsong Ji2019-09-134-444/+0
* [PowerPC][MCP][NFC] Pre-commit test cases for https://reviews.llvm.org/D65267Kai Luo2019-09-121-0/+281
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet2019-09-112-3/+3
* [PowerPC][Peephole] Check if `extsw`'s second operand is a virtual registerKai Luo2019-08-021-2/+3
* [PowerPC][NFC] Precommit a test case where ppc-mi-peepholes miscompiles extswsliKai Luo2019-07-221-0/+66
* [Power9] Allow gpr callee saved spills in prologue to vectors registersZaara Syeda2018-11-091-0/+62
* [if-converter] Handle BBs that terminate in ret during diamond conversionKrzysztof Parzyszek2018-04-191-0/+34
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-6/+6
* MIRParser/MIRPrinter: Compute isSSA instead of printing/parsing it.Matthias Braun2016-08-241-1/+0
* llc: Add support for -run-pass noneMatthias Braun2016-07-161-1/+1
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
* When printing MIR, output to errs() rather than outs().Justin Lebar2016-02-191-1/+1
* Fix PR 24724 - The implicit register verifier shouldn't assume certain operandAlex Lorenz2015-09-102-0/+47
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