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path: root/llvm/test/CodeGen/MIR/AArch64
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* [MIRNamer]: Make the check lines in the test robust with regex.Aditya Nandakumar2019-11-163-29/+29
* [MirNamer][Canonicalizer]: Perform instruction semantic based renamingAditya Nandakumar2019-11-153-32/+32
* [Alignment] Use llvm::Align in MachineFunction and TargetLowering - fixes mir...Guillaume Chatelet2019-09-113-4/+4
* [MIR] Change test case to read from stdin instead of fileMikael Holmen2019-09-061-1/+1
* [MIR] MIRNamer pass for improving MIR test authoring experience.Puyan Lotfi2019-09-051-0/+90
* [mir-canon][NFC] Adding -verify-machineinstrs to mir-canon tests.Puyan Lotfi2019-09-052-9/+10
* GlobalISel: Add more verifier checks for G_SHUFFLE_VECTORMatt Arsenault2019-08-131-9/+9
* GlobalISel: Change representation of shuffle masksMatt Arsenault2019-08-135-0/+248
* Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault2019-06-191-1/+1
* Describe stack-id as an enumSander de Smalen2019-06-173-15/+15
* [MIR-Canon] Skip the first N vreg names lazily.Puyan Lotfi2019-05-311-0/+3
* [MIR-Canon] Fixing case where MachineFunction is empty.Puyan Lotfi2019-05-301-0/+11
* [MIR-Canon] Add support for rewriting VRegs that are typed but don't have an RC.Puyan Lotfi2019-05-301-0/+1
* MIR: Validate LLT types when parsingMatt Arsenault2019-02-047-0/+72
* GlobalISel: Verify load/store has a pointer inputMatt Arsenault2019-01-271-23/+0
* Re-apply "r351584: "GlobalISel: Verify g_zextload and g_sextload""Amara Emerson2019-01-271-0/+23
* Revert r351584: "GlobalISel: Verify g_zextload and g_sextload"Amara Emerson2019-01-191-23/+0
* GlobalISel: Verify g_zextload and g_sextloadMatt Arsenault2019-01-181-0/+23
* [Dwarf/AArch64] Return address signing B key dwarf supportLuke Cheeseman2018-12-211-0/+48
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-12-181-0/+2
* Revert r347490 as it breaks address sanitizer buildsLuke Cheeseman2018-11-231-2/+0
* Revert r343341Luke Cheeseman2018-11-231-0/+2
* Revert r343317Luke Cheeseman2018-09-281-2/+0
* Reapply changes reverted by r343235Luke Cheeseman2018-09-281-0/+2
* Revert r343192 as an ubsan build is currently failingLuke Cheeseman2018-09-271-2/+0
* Reapply changes reverted in r343114, lldb patch to follow shortlyLuke Cheeseman2018-09-271-0/+2
* Revert r343112 as CallFrameString API change has broken lldb buildsLuke Cheeseman2018-09-261-2/+0
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-09-261-0/+2
* Revert r343089 "[AArch64] - Return address signing dwarf support"Hans Wennborg2018-09-261-2/+0
* [AArch64] - Return address signing dwarf supportLuke Cheeseman2018-09-261-0/+2
* [NFC] MIR-Canon: switching to a stable string sorting of instructions.Puyan Lotfi2018-05-131-3/+4
* [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)Roman Tereshin2018-05-085-0/+51
* [MIR] Reset unique MBB numbering in MachineFunction::reset()Roman Tereshin2018-04-301-2/+7
* [MIR] Add support for debug metadata for fixed stack objectsFrancis Visoiu Mistrih2018-04-253-15/+30
* [MIR-Canon] Adding ISA-Agnostic COPY Folding.Puyan Lotfi2018-04-161-0/+45
* [MIR-Canon] Improving performance by switching to named vregs.Puyan Lotfi2018-04-051-5/+5
* [MIR-Canon] Adding support for local idempotent instruction hoisting.Puyan Lotfi2018-03-311-0/+116
* [MIR] Adding support for Named Virtual Registers in MIR.Puyan Lotfi2018-03-301-0/+26
* [MIRParser] Accept overloaded intrinsic names w/o type suffixesRoman Tereshin2018-02-281-0/+24
* [GlobalISel] Print/Parse FailedISel MachineFunction propertyRoman Tereshin2018-02-281-0/+65
* [GISel]: Verify COPIES involving generic registers.Aditya Nandakumar2018-02-091-2/+2
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-3114-64/+64
* [MIR] Add support for addrspace in MIRFrancis Visoiu Mistrih2018-01-261-0/+31
* Move tests to the correct placeMatthias Braun2018-01-191-82/+0
* [MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.Puyan Lotfi2018-01-101-5/+5
* [MIR] Add support for missing CFI directivesFrancis Visoiu Mistrih2017-12-151-34/+23
* [CodeGen] Print "%vreg0" as "%0" in both MIR and debug outputFrancis Visoiu Mistrih2017-11-301-1/+1
* [mir] Print/Parse both MOLoad and MOStore when they occur together.Daniel Sanders2017-11-281-0/+33
* [AsmPrinterDwarf] Add support for .cfi_restore directiveFrancis Visoiu Mistrih2017-11-022-31/+59
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-243-9/+9
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