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* [Hexagon] Restrict compound instructions with constant value.Sumanth Gundapaneni2018-10-111-0/+52
| | | | | | | | | | Having a constant value operand in the compound instruction is not always profitable. This patch improves coremark by ~4% on Hexagon. Differential Revision: https://reviews.llvm.org/D53152 llvm-svn: 344284
* [DAGCombine] Improve Load-Store ForwardingNirav Dave2018-10-103-146/+1
| | | | | | | | | | | | | | | | | | Summary: Extend analysis forwarding loads from preceeding stores to work with extended loads and truncated stores to the same address so long as the load is fully subsumed by the store. Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are deleted as they've no longer seem to be relevant. Reviewers: RKSimon, rnk, kparzysz, javed.absar Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D49200 llvm-svn: 344142
* [Hexagon] Fix extracting subvectors of non-HVX vNi1Krzysztof Parzyszek2018-10-021-0/+28
| | | | | | Patch by Brendon Cahoon. llvm-svn: 343596
* [Hexagon] Remove incorrect pattern for swizKrzysztof Parzyszek2018-10-011-51/+0
| | | | | | | | | | | | The pattern had a couple of problems: - It was checking for loads of bytes in the reverse order to what it should have been looking for. - It would replace loads of bytes with a load of a word without making sure that the alignment was correct. Thanks to Eli Friedman for pointing it out. llvm-svn: 343514
* [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defsBjorn Pettersson2018-09-201-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
* Copy utilities updated and added for MI flagsMichael Berg2018-09-191-1/+1
| | | | | | | | | | | | | | Summary: This patch adds a GlobalIsel copy utility into MI for flags and updates the instruction emitter for the SDAG path. Some tests show new behavior and I added one for GlobalIsel which mirrors an SDAG test for handling nsw/nuw. Reviewers: spatel, wristow, arsenm Reviewed By: arsenm Subscribers: wdng Differential Revision: https://reviews.llvm.org/D52006 llvm-svn: 342576
* [PostRASink] Make sure to remove subregisters from live-ins as wellKrzysztof Parzyszek2018-09-181-0/+33
| | | | llvm-svn: 342492
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+121
| | | | | | | | Shufflevector instructions in LLVM IR that extract a subset of elements of a longer input into a shorter vector can be done using VECTOR_SHUFFLEs. This will avoid expanding them into constly extracts and inserts. llvm-svn: 342091
* [Hexagon] [Test] Remove undef and infinite loop from testRoman Lebedev2018-09-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The undef and the infinite loop at the end cause this test to be translated unpredictably. In particular, the checked-for `mpy` disappears under certain legal optimizations (e.g. the one in D50222). Since the use of these constructs is not relevant to the behavior tested, according to the header comment, this change, suggested by @kparzysz, eliminates them. Was initially committed in r341046, but was reverted. Patch by: hermord (Dmytro Shynkevych)! Reviewers: kparzysz Reviewed By: kparzysz Subscribers: lebedev.ri, llvm-commits, kparzysz Differential Revision: https://reviews.llvm.org/D50944 llvm-svn: 341943
* Add support for getRegisterByName.Sid Manning2018-09-071-0/+13
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341658
* [Hexagon] Don't packetize new-value stores with any other storesKrzysztof Parzyszek2018-09-041-0/+25
| | | | llvm-svn: 341409
* Revert [Hexagon] Add support for getRegisterByName.Sid Manning2018-09-031-23/+0
| | | | | | Support required to build the Hexagon Linux kernel. llvm-svn: 341331
* [Hexagon] Add support for getRegisterByName.Sid Manning2018-08-311-0/+23
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341238
* [Hexagon] Check validity of register class when generating bitsplitKrzysztof Parzyszek2018-08-301-0/+40
| | | | llvm-svn: 341137
* Revert "[Hexagon][Test] Remove undef and infinite loop from test"Roman Lebedev2018-08-301-3/+3
| | | | | | | | | | | | | | | Bots are unhappy: /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm/test/CodeGen/Hexagon/swp-const-tc2.ll:10:14: error: CHECK-NOT: excluded string found in input ; CHECK-NOT: = mpy ^ <stdin>:22:6: note: found here r5 += mpyi(r2,r3) ^~~~~ This reverts commit r341046. llvm-svn: 341049
* [Hexagon][Test] Remove undef and infinite loop from testRoman Lebedev2018-08-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: As suggested in D50222, this has been refactored into a separate patch. The undef and the infinite loop at the end cause this test to be translated unpredictably. In particular, the checked-for `mpy` disappears under certain legal optimizations (e.g. the one in D50222). Since the use of these constructs is not relevant to the behavior tested, according to the header comment, this change, suggested by @kparzysz, eliminates them. Patch by: hermord (Dmytro Shynkevych)! Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits, kparzysz Differential Revision: https://reviews.llvm.org/D50944 llvm-svn: 341046
* [Pipeliner] Fix incorrect phi values in the epilog and kernelBrendon Cahoon2018-08-271-0/+33
| | | | | | | | | | | | | | | | | | | The code that generates the loop definition operand for phis in the epilog and kernel is incorrect in some cases. In the kernel, when a phi refers to another phi, the code that updates PhiOp2 needs to include the stage difference between the two phis. In the epilog, the check for using the loop definition instead of the phi definition uses the StageDiffAdj value (the difference between the phi stage and the loop definition stage), but the adjustment is not needed to determine if the current stage contains an iteration with the loop definition. Differential Revision: https://reviews.llvm.org/D51167 llvm-svn: 340782
* [CodeGen] Set FrameSetup/FrameDestroy on BUNDLE instructionsBjorn Pettersson2018-08-251-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If any of the bundled instructions are marked as FrameSetup or FrameDestroy, then that property is set on the BUNDLE instruction as well. As long as the scheduler/packetizer aren't mixing prologue/epilogue instructions (i.e. all the bundled instructions have the same property) then this simply gives the bundle the correct property (so when using a bundle iterator in late passes a bundle will be correctly identified as FrameSetup/FrameDestroy). When for example bundling a mix of FrameSetup instructions with non-FrameSetup instructions it could be discussed if the bundle should have the property or not. The choice here has been to set these properties on the BUNDLE instruction if any of the bundled instructions have the property set. Reviewers: #debug-info, kparzysz Reviewed By: kparzysz Subscribers: vsk, thegameg, llvm-commits Differential Revision: https://reviews.llvm.org/D50637 llvm-svn: 340680
* [Hexagon] Enable interleaving in loop vectorizerKrzysztof Parzyszek2018-08-221-0/+52
| | | | llvm-svn: 340447
* Change how finalizeBundle selects debug location for the BUNDLE instructionBjorn Pettersson2018-08-211-0/+58
| | | | | | | | | | | | | | | | | | | | | | Summary: Previously a BUNDLE instruction inherited the DebugLoc from the first instruction in the bundle, even if that DebugLoc had no DILocation. With this commit this is changed into selecting the first DebugLoc that has a DILocation, by searching among the bundled instructions. The idea is to reduce amount of bundles that are lacking debug locations. Reviewers: #debug-info, JDevlieghere Reviewed By: JDevlieghere Subscribers: JDevlieghere, mattd, llvm-commits Differential Revision: https://reviews.llvm.org/D50639 llvm-svn: 340267
* [Hexagon] Expand vgather pseudos during packetizationKrzysztof Parzyszek2018-08-172-3/+34
| | | | | | This will allow packetizing the vgather expansion with other instructions. llvm-svn: 340028
* [Hexagon] Map ISD::TRAP to J2_trap0(#0)Krzysztof Parzyszek2018-08-091-1/+1
| | | | llvm-svn: 339365
* [Hexagon] Diagnose misaligned absolute loads and storesKrzysztof Parzyszek2018-08-082-0/+76
| | | | | | Differential Revision: https://reviews.llvm.org/D50405 llvm-svn: 339272
* [Hexagon] Allow use of gather intrinsics even with no-packetsKrzysztof Parzyszek2018-08-071-5/+26
| | | | | | | | | Vgather requires must be in a packet with a store, which contradicts the no-packets feature. As a consequence, gather/scatter could not be used with no-packets. Relax this, and allow gather packets as exceptions to the no-packets requirements. llvm-svn: 339177
* [Hexagon] Simplify CFG after atomic expansionKrzysztof Parzyszek2018-08-0278-706/+576
| | | | | | | | | | This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
* [Hexagon] Simplify A4_rcmp[n]eqi R, 0Krzysztof Parzyszek2018-07-301-0/+154
| | | | | | | Consider cases when register R is known to be zero/non-zero, or when it is defined by a C2_muxii instruction. llvm-svn: 338251
* [Hexagon] Properly scale bit index when extracting elements from vNi1Krzysztof Parzyszek2018-07-251-0/+18
| | | | | | | | For example v = <2 x i1> is represented as bbbbaaaa in a predicate register, where b = v[1], a = v[0]. Extracting v[1] is equivalent to extracting bit 4 from the predicate register. llvm-svn: 337934
* [Hexagon] Handle unnamed globals in HexagonConstExprKrzysztof Parzyszek2018-07-231-0/+38
| | | | | | Instead of comparing names, compare positions in the parent module. llvm-svn: 337723
* [Hexagon] Disable packets in test to avoid ordering issues in checksKrzysztof Parzyszek2018-07-201-2/+2
| | | | llvm-svn: 337624
* [Hexagon] Avoid introducing calls into coalesced range of HVX vector pairsKrzysztof Parzyszek2018-07-131-0/+26
| | | | | | | | | | | | | If an HVX vector register is to be coalesced into a vector pair, make sure that the vector pair will not have a function call in its live range, unless it already had one. All HVX vector registers are volatile, so any vector register live across a function call will have to be spilled. If a vector needs to be spilled, and it's coalesced into a vector pair then the whole pair will need to be spilled (even if only a part of it is live), taking extra stack space. llvm-svn: 337073
* [Hexagon] Change .mir testcase to make sure function is not in SSA formKrzysztof Parzyszek2018-07-101-0/+1
| | | | | | | | | If a machine function satisfies SSA, the IsSSA property is assumed even if the pass to be executed runs after existing from SSA. If the pass output then does not conform to SSA, a verifier error will be flagged (with expensive checks enabled). llvm-svn: 336682
* [Hexagon] Add implicit uses even when untied explicit uses are presentKrzysztof Parzyszek2018-07-101-0/+24
| | | | | | | | | | | | | | | | | | An explicit untied use is not sufficient to maintain liveness of a register redefined in a predicated instruction. For example %1 = COPY %0 ... %1 = A2_paddif %2, %1, 1 could become $r1 = COPY $r0 ... $r1 = A2_paddif $p0, $r1, 1 and later $r1 = COPY $r0 ;; this is not really dead! ... $r1 = A2_paddif $p0, $r0, 1 llvm-svn: 336662
* [DAGCombiner] Ensure we use the correct CC result type in visitSDIV (REAPPLIED)Simon Pilgrim2018-06-281-0/+14
| | | | | | | | | | We could get away with it for constant folded cases, but not for rL335719. Thanks to Krzysztof Parzyszek for noticing. Reapply original commit rL335821 which was reverted at rL335871 due to a WebAssembly bug that was fixed at rL335884. llvm-svn: 335886
* Revert "[DAGCombiner] Ensure we use the correct CC result type in visitSDIV"Haojian Wu2018-06-281-14/+0
| | | | | | | | This reverts commit r335821. This crashes the webassembly test, run "ninja check-llvm-codegen-webassembly" to reproduce. llvm-svn: 335871
* [DAGCombiner] Ensure we use the correct CC result type in visitSDIVSimon Pilgrim2018-06-281-0/+14
| | | | | | | | We could get away with it for constant folded cases, but not for rL335719. Thanks to Krzysztof Parzyszek for noticing. llvm-svn: 335821
* [Hexagon] Add a "generic" cpuBrendon Cahoon2018-06-261-0/+7
| | | | | | | | | | Add the generic processor for Hexagon so that it can be used with 3rd party programs that create a back-end with the "generic" CPU. This patch also enables the JIT for Hexagon. Differential Revision: https://reviews.llvm.org/D48571 llvm-svn: 335641
* [Hexagon] Replace .ll test for expanding post-ra pesudos with .mirKrzysztof Parzyszek2018-06-202-53/+14
| | | | llvm-svn: 335158
* [Hexagon] Enforce restrictions on packetizing cache instructionsKrzysztof Parzyszek2018-06-191-0/+16
| | | | llvm-svn: 335061
* Remove <undef> from rematerialized full registerKrzysztof Parzyszek2018-06-151-0/+37
| | | | | | | | | | | When coalescing a small register into a subregister of a larger register, if the larger register is rematerialized, the function updateRegDefUses can add an <undef> flag to the rematerialized definition (since it's treating it as only definining the coalesced subregister). While with that assumption doing so is not incorrect, make sure to remove the flag later on after the call to updateRegDefUses. llvm-svn: 334845
* [DAGCombiner] Recognize more patterns for ABSKrzysztof Parzyszek2018-06-121-1/+27
| | | | | | Differential Revision: https://reviews.llvm.org/D47831 llvm-svn: 334553
* [Hexagon] Make floating point operations expensive for vectorizationKrzysztof Parzyszek2018-06-121-0/+91
| | | | llvm-svn: 334508
* [SelectionDAG] Provide default expansion for rotatesKrzysztof Parzyszek2018-06-122-2/+207
| | | | | | | | | | | | | Implement default legalization of rotates: either in terms of the rotation in the opposite direction (if legal), or in terms of shifts and ors. Implement generating of rotate instructions for Hexagon. Hexagon only supports rotates by an immediate value, so implement custom lowering of ROTL/ROTR on Hexagon. If a rotate is not legal, use the default expansion. Differential Revision: https://reviews.llvm.org/D47725 llvm-svn: 334497
* [Hexagon] Late predicate producers cannot be used as dot-new sourcesKrzysztof Parzyszek2018-06-111-0/+26
| | | | llvm-svn: 334426
* [Hexagon] Implement vector-pair zero as V6_vsubw_dvKrzysztof Parzyszek2018-06-061-0/+41
| | | | llvm-svn: 334123
* [Hexagon] Split CTPOP of vector pairsKrzysztof Parzyszek2018-06-061-0/+26
| | | | llvm-svn: 334109
* [Hexagon] Add pattern to generate 64-bit neg instructionKrzysztof Parzyszek2018-06-052-14/+17
| | | | llvm-svn: 334043
* [Hexagon] Add more patterns for generating abs/absp instructionsKrzysztof Parzyszek2018-06-052-14/+57
| | | | llvm-svn: 334038
* [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZKrzysztof Parzyszek2018-06-012-0/+249
| | | | llvm-svn: 333760
* [SelectionDAG] Expand UADDO/USUBO into ADD/SUBCARRY if legal for targetKrzysztof Parzyszek2018-06-013-53/+25
| | | | | | | | | Additionally, implement handling of ADD/SUBCARRY on Hexagon, utilizing the UADDO/USUBO expansion. Differential Revision: https://reviews.llvm.org/D47559 llvm-svn: 333751
* [Hexagon] Use vector align-left when shift amount fits in 3 bitsKrzysztof Parzyszek2018-05-304-56/+28
| | | | | | | This saves an instruction because for align-right the shift amount would need to be put in a register first. llvm-svn: 333543
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