[DAGCombine] Improve Load-Store Forwarding

Summary:
Extend analysis forwarding loads from preceeding stores to work with
extended loads and truncated stores to the same address so long as the
load is fully subsumed by the store.

Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are
deleted as they've no longer seem to be relevant.

Reviewers: RKSimon, rnk, kparzysz, javed.absar

Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits

Differential Revision: https://reviews.llvm.org/D49200

llvm-svn: 344142

3 files changed, 1 insertions, 146 deletions

diff --git a/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll b/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
index 9318f2d8a6b..43c866c7b76 100644
--- a/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
+++ b/llvm/test/CodeGen/Hexagon/clr_set_toggle.ll
@@ -70,7 +70,7 @@ entry:
 define zeroext i16 @my_setbit(i16 zeroext %crc) nounwind {
 entry:
 ; CHECK-LABEL: my_setbit
-; CHECK: memh(r{{[0-9]+}}+#{{[0-9]+}}) = setbit(#15)
+; CHECK: r{{[0-9]+}} = setbit(r{{[0-9]+}},#15)
   %crc.addr = alloca i16, align 2
   store i16 %crc, i16* %crc.addr, align 2
   %0 = load i16, i16* %crc.addr, align 2
diff --git a/llvm/test/CodeGen/Hexagon/swp-epilog-phis.ll b/llvm/test/CodeGen/Hexagon/swp-epilog-phis.ll
deleted file mode 100644
index 1073f1c46b1..00000000000
--- a/llvm/test/CodeGen/Hexagon/swp-epilog-phis.ll
+++ /dev/null
@@ -1,55 +0,0 @@
-; RUN: llc -march=hexagon -enable-pipeliner -pipeliner-max-stages=2 \
-; RUN:     -pipeliner-ignore-recmii -disable-hexagon-nv-schedule \
-; RUN:     -hexagon-initial-cfg-cleanup=0 -stats -o /dev/null \
-; RUN:     -enable-aa-sched-mi < %s 2>&1 | FileCheck %s --check-prefix=STATS
-; REQUIRES: asserts
-;
-; Test that we generate the correct phis in the last epilog block when
-; allowing multiple stages.
-;
-; STATS: 1 pipeliner        - Number of loops software pipelined
-
-; Function Attrs: nounwind
-define void @f0() #0 {
-b0:
-  br i1 undef, label %b6, label %b1
-
-b1:                                               ; preds = %b0
-  br i1 undef, label %b6, label %b2
-
-b2:                                               ; preds = %b1
-  br label %b4
-
-b3:                                               ; preds = %b4, %b3
-  %v0 = add nsw i32 0, 57344
-  %v1 = trunc i32 %v0 to i16
-  store i16 %v1, i16* null, align 2, !tbaa !0
-  %v2 = getelementptr inbounds i8, i8* null, i32 undef
-  %v3 = load i8, i8* %v2, align 1, !tbaa !4
-  %v4 = zext i8 %v3 to i32
-  %v5 = shl nuw nsw i32 %v4, 6
-  %v6 = add nsw i32 %v5, 57344
-  %v7 = trunc i32 %v6 to i16
-  store i16 %v7, i16* undef, align 2, !tbaa !0
-  br i1 undef, label %b5, label %b3
-
-b4:                                               ; preds = %b5, %b2
-  %v8 = phi i32 [ 0, %b2 ], [ %v9, %b5 ]
-  br label %b3
-
-b5:                                               ; preds = %b3
-  %v9 = add i32 %v8, 1
-  %v10 = icmp eq i32 %v9, undef
-  br i1 %v10, label %b6, label %b4
-
-b6:                                               ; preds = %b5, %b1, %b0
-  ret void
-}
-
-attributes #0 = { nounwind "target-cpu"="hexagonv55" }
-
-!0 = !{!1, !1, i64 0}
-!1 = !{!"short", !2}
-!2 = !{!"omnipotent char", !3}
-!3 = !{!"Simple C/C++ TBAA"}
-!4 = !{!2, !2, i64 0}
diff --git a/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll b/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll
deleted file mode 100644
index bb45eeac140..00000000000
--- a/llvm/test/CodeGen/Hexagon/swp-memrefs-epilog1.ll
+++ /dev/null
@@ -1,90 +0,0 @@
-; RUN: llc -march=hexagon -enable-pipeliner < %s | FileCheck %s
-
-; Test that a store and load, that alias, are not put in the same packet. The
-; pipeliner altered the size of the memrefs for these instructions, which
-; resulted in no order dependence between the instructions in the DAG. No order
-; dependence was added since the size was set to UINT_MAX, but there is a
-; computation using the size that overflowed.
-
-; CHECK: endloop0
-; CHECK: memh([[REG:r([0-9]+)]]+#0) =
-; CHECK: = memh([[REG]]++#2)
-
-; Function Attrs: nounwind
-define signext i16 @f0(i16* nocapture readonly %a0, i16* nocapture readonly %a1) local_unnamed_addr #0 {
-b0:
-  %v0 = alloca [40 x i16], align 8
-  %v1 = bitcast [40 x i16]* %v0 to i8*
-  call void @llvm.lifetime.start.p0i8(i64 80, i8* nonnull %v1) #2
-  %v2 = getelementptr inbounds [40 x i16], [40 x i16]* %v0, i32 0, i32 0
-  br label %b1
-
-b1:                                               ; preds = %b1, %b0
-  %v3 = phi i16* [ %a1, %b0 ], [ %v24, %b1 ]
-  %v4 = phi i16* [ %v2, %b0 ], [ %v25, %b1 ]
-  %v5 = phi i32 [ 0, %b0 ], [ %v14, %b1 ]
-  %v6 = phi i32 [ 1, %b0 ], [ %v22, %b1 ]
-  %v7 = phi i32 [ 0, %b0 ], [ %v23, %b1 ]
-  %v8 = load i16, i16* %v3, align 2
-  %v9 = sext i16 %v8 to i32
-  %v10 = tail call i32 @llvm.hexagon.A2.aslh(i32 %v9)
-  %v11 = tail call i32 @llvm.hexagon.S2.asr.r.r.sat(i32 %v10, i32 1)
-  %v12 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v11)
-  %v13 = trunc i32 %v12 to i16
-  store i16 %v13, i16* %v4, align 2
-  %v14 = add nuw nsw i32 %v5, 1
-  %v15 = icmp eq i32 %v14, 40
-  %v16 = getelementptr inbounds i16, i16* %a0, i32 %v7
-  %v17 = load i16, i16* %v16, align 2
-  %v18 = sext i16 %v17 to i32
-  %v19 = getelementptr inbounds [40 x i16], [40 x i16]* %v0, i32 0, i32 %v7
-  %v20 = load i16, i16* %v19, align 2
-  %v21 = sext i16 %v20 to i32
-  %v22 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v6, i32 %v18, i32 %v21)
-  %v23 = add nuw nsw i32 %v7, 1
-  %v24 = getelementptr i16, i16* %v3, i32 1
-  %v25 = getelementptr i16, i16* %v4, i32 1
-  br i1 %v15, label %b2, label %b1
-
-b2:                                               ; preds = %b1
-  %v26 = tail call signext i16 @f1(i32 %v22) #0
-  %v27 = sext i16 %v26 to i32
-  %v28 = tail call i32 @llvm.hexagon.S2.asl.r.r.sat(i32 %v22, i32 %v27)
-  %v29 = tail call i32 @llvm.hexagon.A2.asrh(i32 %v28)
-  %v30 = shl i32 %v29, 16
-  %v31 = ashr exact i32 %v30, 16
-  %v32 = icmp slt i32 %v30, 65536
-  br label %b3
-
-b3:                                               ; preds = %b2
-  call void @llvm.lifetime.end.p0i8(i64 80, i8* nonnull %v1) #2
-  ret i16 0
-}
-
-; Function Attrs: argmemonly nounwind
-declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.hexagon.S2.asr.r.r.sat(i32, i32) #2
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.hexagon.A2.aslh(i32) #2
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.hexagon.A2.asrh(i32) #2
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32, i32, i32) #2
-
-; Function Attrs: nounwind
-declare signext i16 @f1(i32) local_unnamed_addr #0
-
-; Function Attrs: nounwind readnone
-declare i32 @llvm.hexagon.S2.asl.r.r.sat(i32, i32) #2
-
-; Function Attrs: argmemonly nounwind
-declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
-
-attributes #0 = { nounwind }
-attributes #1 = { argmemonly nounwind }
-attributes #2 = { nounwind readnone }