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* [Hexagon] Skip mux generation when predicate register is undefinedKrzysztof Parzyszek2017-06-081-0/+27
| | | | llvm-svn: 305014
* [Hexagon] Generate 'inbounds' GEPs in HexagonCommonGEPKrzysztof Parzyszek2017-06-071-0/+20
| | | | llvm-svn: 304937
* [Hexagon] Return 0 from getDotNewPredOp when .new opcode does not existKrzysztof Parzyszek2017-06-021-0/+44
| | | | | | | This allows using this function to test if an instruction can be converted to a .new form. llvm-svn: 304549
* [Hexagon] Fix dependence check in the packetizerKrzysztof Parzyszek2017-06-011-0/+17
| | | | | | | An incorrect check in the packetizer lead to an attempt to convert an unconditional branch to a .new (conditional) form. llvm-svn: 304442
* [Hexagon] Handle long-running simplification loop in idiom recognitionKrzysztof Parzyszek2017-06-011-0/+62
| | | | | | | | | | | | | The initial assumption was that the simplification would converge to a fixed point relatvely quickly. Turns out that there are legitimate situa- tions where the complexity of the code causes it to take a large number of iterations. Two main changes: - Instead of aborting upon hitting the limit, simply return nullptr. - Reduce the limit to 10,000 from 100,000. llvm-svn: 304441
* [Hexagon] Improve code generation for 32x32-bit multiplicationKrzysztof Parzyszek2017-05-301-0/+93
| | | | | | | | | For multiplications of 64-bit values (giving 64-bit result), detect cases where the arguments are sign-extended 32-bit values, on a per- operand basis. This will allow few patterns to match a wider variety of combinations in which extensions can occur. llvm-svn: 304223
* ScheduleDAGInstrs: Fix fixupKills()Matthias Braun2017-05-271-1/+1
| | | | | | | | | | | | Rewrite fixupKills() to use the LivePhysRegs class. Simplifies the code and fixes a bug where the CSR registers in return blocks where missed leading to invalid kill flags. Also remove the unnecessary rule that we wouldn't set kill flags on tied operands. No tests as I have an upcoming commit improving MachineVerifier checks to catch these cases in multiple existing lit tests. llvm-svn: 304055
* Add extra operand to CALLSEQ_START to keep frame part set up previouslySerge Pavlov2017-05-091-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using arguments with attribute inalloca creates problems for verification of machine representation. This attribute instructs the backend that the argument is prepared in stack prior to CALLSEQ_START..CALLSEQ_END sequence (see http://llvm.org/docs/InAlloca.htm for details). Frame size stored in CALLSEQ_START in this case does not count the size of this argument. However CALLSEQ_END still keeps total frame size, as caller can be responsible for cleanup of entire frame. So CALLSEQ_START and CALLSEQ_END keep different frame size and the difference is treated by MachineVerifier as stack error. Currently there is no way to distinguish this case from actual errors. This patch adds additional argument to CALLSEQ_START and its target-specific counterparts to keep size of stack that is set up prior to the call frame sequence. This argument allows MachineVerifier to calculate actual frame size associated with frame setup instruction and correctly process the case of inalloca arguments. The changes made by the patch are: - Frame setup instructions get the second mandatory argument. It affects all targets that use frame pseudo instructions and touched many files although the changes are uniform. - Access to frame properties are implemented using special instructions rather than calls getOperand(N).getImm(). For X86 and ARM such replacement was made previously. - Changes that reflect appearance of additional argument of frame setup instruction. These involve proper instruction initialization and methods that access instruction arguments. - MachineVerifier retrieves frame size using method, which reports sum of frame parts initialized inside frame instruction pair and outside it. The patch implements approach proposed by Quentin Colombet in https://bugs.llvm.org/show_bug.cgi?id=27481#c1. It fixes 9 tests failed with machine verifier enabled and listed in PR27481. Differential Revision: https://reviews.llvm.org/D32394 llvm-svn: 302527
* [RDF] Remove covered parts of reached uses for phi and use in same blockKrzysztof Parzyszek2017-05-051-0/+38
| | | | llvm-svn: 302305
* Remove stale live-ins in the branch folderKrzysztof Parzyszek2017-05-051-0/+59
| | | | | | | | | | | Hoisting common code can cause registers that live-in in the successor blocks to no longer be live-in. The live-in information needs to be updated to reflect this, or otherwise incorrect code can be generated later on. Differential Revision: https://reviews.llvm.org/D32661 llvm-svn: 302228
* [Hexagon] Use automatically-generated scheduling information for HVXKrzysztof Parzyszek2017-05-031-7/+6
| | | | | | Patch by Jyotsna Verma. llvm-svn: 302073
* [Hexagon] Adjust latency between allocframe and the first store on stackKrzysztof Parzyszek2017-05-031-0/+81
| | | | | | | | | | | | Allocframe and the following stores on the stack have a latency of 2 cycles when not in the same packet. This happens because R29 is needed early by the store instruction. Since one of such stores can be packetized along with allocframe and use old value of R29, we can assign it 0 cycle latency while leaving latency of other stores to the default value of 2 cycles. Patch by Jyotsna Verma. llvm-svn: 302034
* [Hexagon] Add extenders for GD_PLT_B22_PCREL and LD_PLT_B22_PCRELKrzysztof Parzyszek2017-05-021-0/+37
| | | | | | Patch by Sid Manning. llvm-svn: 301955
* [Hexagon] Don't ignore mult-cycle latency informationKrzysztof Parzyszek2017-05-021-0/+103
| | | | | | | | | | | | | | | | | | | | | | | | The compiler was generating code that ends up ignoring a multiple latency dependence between two instructions by scheduling the intructions in back-to-back packets. The packetizer needs to end a packet if the latency of the current current insruction and the source in the previous packet is greater than 1 cycle. This case occurs when there is still room in the current packet, but scheduling the instruction causes a stall. Instead, the packetizer should start a new packet. Also, if the current packet already contains a stall, then it is okay to add another instruction to the packet that also causes a stall. This occurs when there are no instructions that can be scheduled in between the producer and consumer instructions. This patch changes the latency for loads to 2 cycles from 3 cycles. This change refects that a load only needs to be separated by one extra packet to eliminate the stall. Patch by Ikhlas Ajbar. llvm-svn: 301954
* [RDF] Correctly calculate lane masks for defsKrzysztof Parzyszek2017-04-281-0/+52
| | | | llvm-svn: 301700
* Properly handle PHIs with subregisters in UnreachableBlockElimKrzysztof Parzyszek2017-04-281-0/+25
| | | | | | | | | When a PHI operand has a subregister, create a COPY instead of simply replacing the PHI output with the input it. Differential Revision: https://reviews.llvm.org/D32650 llvm-svn: 301699
* [Hexagon] Do not move a block if it is on a fall-through pathKrzysztof Parzyszek2017-04-281-0/+71
| | | | llvm-svn: 301698
* [Hexagon] Generate proper offset in opt-addr-modeKrzysztof Parzyszek2017-04-191-0/+25
| | | | | | | | | Also, make a few changes to allow using the pass in .mir testcases. Among other things, change the abbreviation from opt-amode to amode-opt, because otherwise lit would expand the "opt" part to the full path to the opt binary. llvm-svn: 300707
* Add address space mangling to lifetime intrinsicsMatt Arsenault2017-04-108-46/+46
| | | | | | In preparation for allowing allocas to have non-0 addrspace. llvm-svn: 299876
* [Hexagon] Use -mattr to select HVX mode in a testcase, NFCKrzysztof Parzyszek2017-04-051-3/+2
| | | | llvm-svn: 299582
* [Hexagon] Fix typo in HexagonEarlyIfCConv.cppKrzysztof Parzyszek2017-03-311-1/+1
| | | | | | Found by PVS-Studio. Fixes llvm.org/PR32480. llvm-svn: 299258
* [Hexagon] Avoid infinite loops in HexagonLoopIdiomRecognitionKrzysztof Parzyszek2017-03-231-0/+83
| | | | | | | | | - Avoid explosive growth of the simplification queue by not queuing expressions that are alredy in it. - Add an iteration counter and abort after a sufficiently large number of iterations (assuming that it's a symptom of an infinite loop). llvm-svn: 298655
* Recommit r298282 with fixes for memory allocation/deallocationKrzysztof Parzyszek2017-03-211-0/+84
| | | | | | | | | | | [Hexagon] Recognize polynomial-modulo loop idiom again Regain the ability to recognize loops calculating polynomial modulo operation. This ability has been lost due to some changes in the preceding optimizations. Add code to preprocess the IR to a form that the pattern matching code can recognize. llvm-svn: 298400
* [Hexagon] Add -march=hexagon to a testcaseKrzysztof Parzyszek2017-03-211-1/+1
| | | | llvm-svn: 298395
* Revert "[Hexagon] Recognize polynomial-modulo loop idiom again"Vitaly Buka2017-03-211-84/+0
| | | | | | | | Fix memory leaks on check-llvm tests detected by Asan. This reverts commit r298282. llvm-svn: 298329
* [Hexagon] Recognize polynomial-modulo loop idiom againKrzysztof Parzyszek2017-03-201-0/+84
| | | | | | | | | Regain the ability to recognize loops calculating polynomial modulo operation. This ability has been lost due to some changes in the preceding optimizations. Add code to preprocess the IR to a form that the pattern matching code can recognize. llvm-svn: 298282
* [RDF] Remove the map of reaching defs from copy propagationKrzysztof Parzyszek2017-03-101-2/+2
| | | | | | Use Liveness::getNearestAliasedRef to find the reaching def instead. llvm-svn: 297526
* [Hexagon] Fixes to the bitsplit generationKrzysztof Parzyszek2017-03-091-0/+33
| | | | | | | | - Fix the insertion point, which occasionally could have been incorrect. - Avoid creating multiple bitsplits with the same operands, if an old one could be reused. llvm-svn: 297414
* [Hexagon] Propagate zext of i1 into arithmetic code in selection DAGKrzysztof Parzyszek2017-03-093-54/+60
| | | | | | | (op ... (zext i1 c) ...) -> (select c (op ... 1 ...), (op ... 0 ...)) llvm-svn: 297391
* [Hexagon] Use correct offset when extracting from the high wordKrzysztof Parzyszek2017-03-081-0/+23
| | | | | | | | When extracting a bitfield from the high register in a register pair, the final offset should be relative to the high register (for 32-bit extracts). llvm-svn: 297288
* [Hexagon] Check for presence before looking registers up in bit trackerKrzysztof Parzyszek2017-03-071-0/+64
| | | | llvm-svn: 297240
* [Hexagon] Generate bitsplit instructionKrzysztof Parzyszek2017-03-072-0/+52
| | | | llvm-svn: 297239
* [Hexagon] Do not insert instructions before PHI nodesKrzysztof Parzyszek2017-03-071-0/+1
| | | | llvm-svn: 297141
* Revert r297039, it's causing some mysterious buildbot failuresKrzysztof Parzyszek2017-03-061-27/+0
| | | | llvm-svn: 297062
* [IfConversion] Only renormalize probabilities if branches are analyzableKrzysztof Parzyszek2017-03-061-0/+36
| | | | | | | | | | | If a block has non-analyzable branches, the listed successors don't need to add up to one. For example, if a block has a conditional tail call, that tail call will not have a corresponding successor in the successor list, but will still be a possible branch. Differential Revision: https://reviews.llvm.org/D30556 llvm-svn: 297054
* [TableGen] Ensure proper ordering of subtarget feature namesKrzysztof Parzyszek2017-03-061-0/+27
| | | | llvm-svn: 297039
* [Hexagon] Early-if-convert branches that may exit the loopKrzysztof Parzyszek2017-03-062-1/+92
| | | | | | | | | | | | | | | | Merge the tail block into the loop in cases where the main loop body exits early, subject to profitability constraints. This will coalesce the loop body into fewer blocks. For example: loop: loop: // loop body // loop body if (...) jump exit --> // more body more: if (...) jump exit // more body jump loop jump loop llvm-svn: 297033
* [Hexagon] Mark dead defs as <dead> in expand-condsetsKrzysztof Parzyszek2017-03-062-0/+99
| | | | | | | | | The code in updateDeadFlags removed unnecessary <dead> flags, but there can be cases where such a flag is not set, and yet a register has become dead. For example, if a mux with identical inputs is replaced with a COPY, the predicate register may no longer be used after that. llvm-svn: 297032
* [Hexagon] Pick a dot-old instruction that matches the architectureKrzysztof Parzyszek2017-03-061-0/+110
| | | | llvm-svn: 297031
* [Hexagon] Pick the right branch opcode depending on branch probabilitiesKrzysztof Parzyszek2017-03-021-0/+44
| | | | | | | Specifically, pick the opcode with the correct branch prediction, i.e. jump:t or jump:nt. llvm-svn: 296821
* [Hexagon] Skip blocks that define vector predicate registers in early-ifKrzysztof Parzyszek2017-03-021-0/+37
| | | | llvm-svn: 296777
* [Hexagon] Properly handle 'q' constraint in 128-byte vector modeKrzysztof Parzyszek2017-03-021-0/+15
| | | | llvm-svn: 296772
* [Hexagon] Fix lowering of formal arguments of type i1Krzysztof Parzyszek2017-03-011-0/+6
| | | | | | | | | | | On Hexagon, values of type i1 are passed in registers of type i32, even though i1 is not a legal value for these registers. This is a special case and needs special handling to maintain consistency of the lowering information. This fixes PR32089. llvm-svn: 296645
* [Hexagon] Generate extract instructions more aggressivelyKrzysztof Parzyszek2017-02-284-3/+81
| | | | llvm-svn: 296537
* [Hexagon] Fix instruction selection for sign-extending i1 to i64Krzysztof Parzyszek2017-02-281-0/+22
| | | | llvm-svn: 296532
* [Hexagon] Undo shift folding where it could simplify addressing modeKrzysztof Parzyszek2017-02-241-0/+59
| | | | | | | | | | | | For example, avoid (single shift): r0 = and(##536870908,lsr(r0,#3)) r0 = memw(r1+r0<<#0) in favor of (two shifts): r0 = lsr(r0,#5) r0 = memw(r1+r0<<#2) llvm-svn: 296196
* [DAGCombiner] add missing folds for scalar select of {-1,0,1}Sanjay Patel2017-02-242-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | The motivation for filling out these select-of-constants cases goes back to D24480, where we discussed removing an IR fold from add(zext) --> select. And that goes back to: https://reviews.llvm.org/rL75531 https://reviews.llvm.org/rL159230 The idea is that we should always canonicalize patterns like this to a select-of-constants in IR because that's the smallest IR and the best for value tracking. Note that we currently do the opposite in some cases (like the cases in *this* patch). Ie, the proposed folds in this patch already exist in InstCombine today: https://github.com/llvm-mirror/llvm/blob/master/lib/Transforms/InstCombine/InstCombineSelect.cpp#L1151 As this patch shows, most targets generate better machine code for simple ext/add/not ops rather than a select of constants. So the follow-up steps to make this less of a patchwork of special-case folds and missing IR canonicalization: 1. Have DAGCombiner convert any select of constants into ext/add/not ops. 2 Have InstCombine canonicalize in the other direction (create more selects). Differential Revision: https://reviews.llvm.org/D30180 llvm-svn: 296137
* [Hexagon] Handle saturations in Hexagon bit trackerKrzysztof Parzyszek2017-02-231-0/+57
| | | | llvm-svn: 296026
* [Hexagon] Avoid IMPLICIT_DEFs as new-value producersKrzysztof Parzyszek2017-02-231-0/+79
| | | | llvm-svn: 295997
* [Hexagon] Patterns for CTPOP, BSWAP and BITREVERSEKrzysztof Parzyszek2017-02-232-36/+135
| | | | llvm-svn: 295981
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