[Hexagon] Improve code generation for 32x32-bit multiplication

For multiplications of 64-bit values (giving 64-bit result), detect
cases where the arguments are sign-extended 32-bit values, on a per-
operand basis. This will allow few patterns to match a wider variety
of combinations in which extensions can occur.

llvm-svn: 304223

1 files changed, 93 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/mul64-sext.ll b/llvm/test/CodeGen/Hexagon/mul64-sext.ll
new file mode 100644
index 00000000000..8bbe6649a1f
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/mul64-sext.ll
@@ -0,0 +1,93 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+target triple = "hexagon-unknown--elf"
+
+; CHECK-LABEL: mul_1
+; CHECK: r1:0 = mpy(r2,r0)
+define i64 @mul_1(i64 %a0, i64 %a1) #0 {
+b2:
+  %v3 = shl i64 %a0, 32
+  %v4 = ashr exact i64 %v3, 32
+  %v5 = shl i64 %a1, 32
+  %v6 = ashr exact i64 %v5, 32
+  %v7 = mul nsw i64 %v6, %v4
+  ret i64 %v7
+}
+
+; CHECK-LABEL: mul_2
+; CHECK: r0 = memb(r0+#0)
+; CHECK: r1:0 = mpy(r2,r0)
+; CHECK: jumpr r31
+define i64 @mul_2(i8* %a0, i64 %a1) #0 {
+b2:
+  %v3 = load i8, i8* %a0
+  %v4 = sext i8 %v3 to i64
+  %v5 = shl i64 %a1, 32
+  %v6 = ashr exact i64 %v5, 32
+  %v7 = mul nsw i64 %v6, %v4
+  ret i64 %v7
+}
+
+; CHECK-LABEL: mul_acc_1
+; CHECK: r5:4 += mpy(r2,r0)
+; CHECK: r1:0 = combine(r5,r4)
+; CHECK: jumpr r31
+define i64 @mul_acc_1(i64 %a0, i64 %a1, i64 %a2) #0 {
+b3:
+  %v4 = shl i64 %a0, 32
+  %v5 = ashr exact i64 %v4, 32
+  %v6 = shl i64 %a1, 32
+  %v7 = ashr exact i64 %v6, 32
+  %v8 = mul nsw i64 %v7, %v5
+  %v9 = add i64 %a2, %v8
+  ret i64 %v9
+}
+
+; CHECK-LABEL: mul_acc_2
+; CHECK: r2 = memw(r2+#0)
+; CHECK: r5:4 += mpy(r2,r0)
+; CHECK: r1:0 = combine(r5,r4)
+; CHECK: jumpr r31
+define i64 @mul_acc_2(i64 %a0, i32* %a1, i64 %a2) #0 {
+b3:
+  %v4 = shl i64 %a0, 32
+  %v5 = ashr exact i64 %v4, 32
+  %v6 = load i32, i32* %a1
+  %v7 = sext i32 %v6 to i64
+  %v8 = mul nsw i64 %v7, %v5
+  %v9 = add i64 %a2, %v8
+  ret i64 %v9
+}
+
+; CHECK-LABEL: mul_nac_1
+; CHECK: r5:4 -= mpy(r2,r0)
+; CHECK: r1:0 = combine(r5,r4)
+; CHECK: jumpr r31
+define i64 @mul_nac_1(i64 %a0, i64 %a1, i64 %a2) #0 {
+b3:
+  %v4 = shl i64 %a0, 32
+  %v5 = ashr exact i64 %v4, 32
+  %v6 = shl i64 %a1, 32
+  %v7 = ashr exact i64 %v6, 32
+  %v8 = mul nsw i64 %v7, %v5
+  %v9 = sub i64 %a2, %v8
+  ret i64 %v9
+}
+
+; CHECK-LABEL: mul_nac_2
+; CHECK: r0 = memw(r0+#0)
+; CHECK: r5:4 -= mpy(r2,r0)
+; CHECK: r1:0 = combine(r5,r4)
+; CHECK: jumpr r31
+define i64 @mul_nac_2(i32* %a0, i64 %a1, i64 %a2) #0 {
+b3:
+  %v4 = load i32, i32* %a0
+  %v5 = sext i32 %v4 to i64
+  %v6 = shl i64 %a1, 32
+  %v7 = ashr exact i64 %v6, 32
+  %v8 = mul nsw i64 %v7, %v5
+  %v9 = sub i64 %a2, %v8
+  ret i64 %v9
+}
+
+attributes #0 = { nounwind }