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* [Pipeliner] Add two pragmas to control software pipelining optimizationBrendon Cahoon2019-01-234-2/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | #pragma clang loop pipeline(disable) Disable SWP optimization for the next loop. “disable” is the only possible value. #pragma clang loop pipeline_initiation_interval(number) Set value of initiation interval for SWP optimization to specified number value for the next loop. Number is the positive value greater than 0. These pragmas could be used for debugging or reducing compile time purposes. It is possible to disable SWP for concrete loops to save compilation time or to find bugs by not doing SWP to certain loops. It is possible to set value of initiation interval to concrete number to save compilation time by not doing extra pipeliner passes or to check created schedule for specific initiation interval. That is llvm part of the fix Clang part of fix: https://reviews.llvm.org/D55710 Patch by Alexey Lapshin! Differential Revision: https://reviews.llvm.org/D56403 llvm-svn: 351923
* Remove irrelevant references to legacy git repositories fromJames Y Knight2019-01-155-9/+9
| | | | | | | | | compiler identification lines in test-cases. (Doing so only because it's then easier to search for references which are actually important and need fixing.) llvm-svn: 351200
* [DAGCombiner] allow narrowing of add followed by truncateSanjay Patel2018-12-221-1/+1
| | | | | | | | | | | | | | | trunc (add X, C ) --> add (trunc X), C' If we're throwing away the top bits of an 'add' instruction, do it in the narrow destination type. This makes the truncate-able opcode list identical to the sibling transform done in IR (in instcombine). This change used to show regressions for x86, but those are gone after D55494. This gets us closer to deleting the x86 custom function (combineTruncatedArithmetic) that does almost the same thing. Differential Revision: https://reviews.llvm.org/D55866 llvm-svn: 350006
* [Hexagon] Add patterns for funnel shiftsKrzysztof Parzyszek2018-12-202-27/+279
| | | | llvm-svn: 349770
* [DAGCombiner] allow hoisting vector bitwise logic ahead of truncatesSanjay Patel2018-12-162-18/+18
| | | | | | | | | | | | | | | | | | The transform performs a bitwise logic op in a wider type followed by truncate when both inputs are truncated from the same source type: logic_op (truncate x), (truncate y) --> truncate (logic_op x, y) There are a bunch of other checks that should prevent doing this when it might be harmful. We already do this transform for scalars in this spot. The vector limitation was shared with a check for the case when the operands are extended. I'm not sure if that limit is needed either, but that would be a separate patch. Differential Revision: https://reviews.llvm.org/D55448 llvm-svn: 349303
* [Hexagon] Add patterns for shifts of v2i16Krzysztof Parzyszek2018-12-141-0/+16
| | | | | | This fixes https://llvm.org/PR39983. llvm-svn: 349202
* [Hexagon] make test immune to scalarization improvements; NFCSanjay Patel2018-12-141-3/+3
| | | | llvm-svn: 349163
* [mir] Serialize DILocation inline when not possible to use a metadata referenceDaniel Sanders2018-12-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Sometimes MIR-level passes create DILocations that were not present in the LLVM-IR. For example, it may merge two DILocations together to produce a DILocation that points to line 0. Previously, the address of these DILocations were printed which prevented the MIR from being read back into LLVM. With this patch, DILocations will use metadata references where possible and fall back on serializing them inline like so: MOV32mr %stack.0.x.addr, 1, _, 0, _, %0, debug-location !DILocation(line: 1, scope: !15) Reviewers: aprantl, vsk, arphaman Reviewed By: aprantl Subscribers: probinson, llvm-commits Tags: #debug-info Differential Revision: https://reviews.llvm.org/D55243 llvm-svn: 349035
* [Hexagon] Couple of fixes in optimize addressing modeKrzysztof Parzyszek2018-12-101-0/+40
| | | | | | | | | | - Check if an operand is an immediate before calling getImm. Some operands that take constant values can actually have global symbols or other constant expressions. - When a load-constant instruction can be folded into users, make sure to only delete it when all users have been successfully converted. llvm-svn: 348802
* Revert "[Hexagon] Check if operand is an immediate before getImm"Krzysztof Parzyszek2018-12-101-40/+0
| | | | | | This reverts r348787. The patch wasn't quite correct. llvm-svn: 348792
* [Hexagon] Check if operand is an immediate before getImmKrzysztof Parzyszek2018-12-101-0/+40
| | | | llvm-svn: 348787
* [Hexagon] Fix post-ra expansion of PS_wselectKrzysztof Parzyszek2018-12-071-0/+13
| | | | llvm-svn: 348655
* [Hexagon] Add intrinsics for Hexagon V66Krzysztof Parzyszek2018-12-051-0/+45
| | | | llvm-svn: 348413
* [Hexagon] Add instruction definitions for Hexagon V66Krzysztof Parzyszek2018-12-052-0/+34
| | | | llvm-svn: 348411
* [Hexagon] Switch to auto-generated intrinsic definitions and patternsKrzysztof Parzyszek2018-12-031-2/+2
| | | | llvm-svn: 348206
* [Hexagon] make test immune to improvements in undef simplificationSanjay Patel2018-11-191-2/+2
| | | | llvm-svn: 347218
* [Hexagon] make tests immune to improvements in undef simplificationSanjay Patel2018-11-183-8/+8
| | | | llvm-svn: 347165
* DAG combiner: fold (select, C, X, undef) -> XStanislav Mekhanoshin2018-11-162-2/+2
| | | | | | Differential Revision: https://reviews.llvm.org/D54646 llvm-svn: 347110
* [Hexagon] Implement noreturn optimizationBrendon Cahoon2018-11-091-0/+94
| | | | | | | | | | | Eliminate the stack frame in functions with the noreturn nounwind attributes, and when the noreturn-stack-elim target feature is enabled. This reduces the code and stack space needed for noreturn functions. Differential Revision: https://reviews.llvm.org/D54210 llvm-svn: 346532
* [Hexagon] Place globals with explicit .sdata section in small dataKrzysztof Parzyszek2018-11-091-0/+6
| | | | | | | | Both -fPIC and -G0 disable placement of globals in small data section, but if a global has an explicit section assigmnent placing it in small data, it should go there anyway. llvm-svn: 346523
* [Hexagon] Do not reduce load size for globals in small-dataKrzysztof Parzyszek2018-11-021-0/+19
| | | | | | | | | | | | Small-data (i.e. GP-relative) loads and stores allow 16-bit scaled offset. For a load of a value of type T, the small-data area is equivalent to an array "T sdata[65536]". This implies that objects of smaller sizes need to be closer to the beginning of sdata, while larger objects may be farther away, or otherwise the offset may be insufficient to reach it. Similarly, an object of a larger size should not be accessed via a load of a smaller size. llvm-svn: 345975
* [MC] Implement EmitRawText in MCNullStreamerDaniel Sanders2018-11-011-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This adds dummy implementation of `EmitRawText` in `MCNullStreamer`. This fixes the behavior of `AsmPrinter` with `MCNullStreamer` on targets on which no integrated assembler is used. An attempt to emit inline asm on such a target would previously lead to a crash, since `AsmPrinter` does not check for `hasRawTextSupport` in `EmitInlineAsm` and calls `EmitRawText` anyway if integrated assembler is disabled (the behavior has changed in D2686). Error message printed by MCStreamer: > EmitRawText called on an MCStreamer that doesn't support it, something > must not be fully mc'ized Patch by Eugene Sharygin Reviewers: dsanders, echristo Reviewed By: dsanders Subscribers: eraman, llvm-commits Differential Revision: https://reviews.llvm.org/D53938 llvm-svn: 345841
* [Hexagon] Make sure not to use GP-relative addressing with PICKrzysztof Parzyszek2018-10-311-0/+37
| | | | | | | Make sure that -relocation-model=pic prevents use of GP-relative addressing modes. llvm-svn: 345731
* MachineOperand/MIParser: Do not print debug-use flag, infer itMatthias Braun2018-10-301-10/+10
| | | | | | | | | | | | | | The debug-use flag must be set exactly for uses on DBG_VALUEs. This is so obvious that it can be trivially inferred while parsing. This will reduce noise when printing while omitting an information that has little value to the user. The parser will keep recognizing the flag for compatibility with old `.mir` files. Differential Revision: https://reviews.llvm.org/D53903 llvm-svn: 345671
* [Pipeliner] Mark swp-art-deps-rec.ll as REQUIRES: asserts after rL345319Fangrui Song2018-10-261-0/+2
| | | | llvm-svn: 345359
* [Pipeliner] Ignore Artificial dependences while computing recurrences.Sumanth Gundapaneni2018-10-251-0/+107
| | | | | | | | | | The artificial dependencies are not real dependencies. In some cases, they form circuits with bigger MII. However, they are used to schedule instructions better. Differential Revision: https://reviews.llvm.org/D53450 llvm-svn: 345319
* Reapply "[MachineCopyPropagation] Reimplement CopyTracker in terms of ↵Justin Bogner2018-10-221-0/+51
| | | | | | | | | | | | | | | | | | | register units" Recommits r342942, which was reverted in r343189, with a fix for an issue where we would propagate unsafely if we defined only the upper part of a register. Original message: Change the copy tracker to keep a single map of register units instead of 3 maps of registers. This gives a very significant compile time performance improvement to the pass. I measured a 30-40% decrease in time spent in MCP on x86 and AArch64 and much more significant improvements on out of tree targets with more registers. llvm-svn: 344942
* [Hexagon] Remove support for V4Krzysztof Parzyszek2018-10-1930-1374/+1352
| | | | llvm-svn: 344791
* [pipeliner] Fix test added in rL344748 to require assertsFangrui Song2018-10-191-0/+2
| | | | llvm-svn: 344775
* [Pipeliner] copyToPhi DAG Mutation to improve scheduling.Sumanth Gundapaneni2018-10-181-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | In a loop, create artificial dependences between the source of a COPY/REG_SEQUENCE to the use in next iteration. Eg: SRC ----Data Dep--> COPY COPY ---Anti Dep--> PHI (implies, to be used in next iteration) PHI ----Data Dep--> USE This patches creates USE ----Artificial Dep---> SRC This will effectively schedule the COPY late to eliminate additional copies. Before this patch, the schedule can be SRC, COPY, USE : The COPY is used in next iteration and it needs to be preserved. After this patch, the schedule can be USE, SRC, COPY : The COPY is used in next iteration and the live interval is reduced. Differential Revision: https://reviews.llvm.org/D53303 llvm-svn: 344748
* [TwoAddressInstructionPass] Replace subregister uses when processing tied ↵Bjorn Pettersson2018-10-151-0/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | operands Summary: TwoAddressInstruction pass typically rewrites %1:short = foo %0.sub_lo:long as %1:short = COPY %0.sub_lo:long %1:short = foo %1:short when having tied operands. If there are extra un-tied operands that uses the same reg and subreg, such as the second and third inputs to fie here: %1:short = fie %0.sub_lo:long, %0.sub_hi:long, %0.sub_lo:long then there was a bug which replaced the register %0 also for the un-tied operand, but without changing the subregister indices. So we used to get: %1:short = COPY %0.sub_lo:long %1:short = fie %1, %1.sub_hi:short, %1.sub_lo:short With this fix we instead get: %1:short = COPY %0.sub_lo:long %1:short = fie %1, %0.sub_hi:long, %1 Reviewers: arsenm, JesperAntonsson, kparzysz, MatzeB Reviewed By: MatzeB Subscribers: bjope, kparzysz, wdng, llvm-commits Differential Revision: https://reviews.llvm.org/D36224 llvm-svn: 344492
* [Hexagon] Restrict compound instructions with constant value.Sumanth Gundapaneni2018-10-111-0/+52
| | | | | | | | | | Having a constant value operand in the compound instruction is not always profitable. This patch improves coremark by ~4% on Hexagon. Differential Revision: https://reviews.llvm.org/D53152 llvm-svn: 344284
* [DAGCombine] Improve Load-Store ForwardingNirav Dave2018-10-103-146/+1
| | | | | | | | | | | | | | | | | | Summary: Extend analysis forwarding loads from preceeding stores to work with extended loads and truncated stores to the same address so long as the load is fully subsumed by the store. Hexagon's swp-epilog-phis.ll and swp-memrefs-epilog1.ll test are deleted as they've no longer seem to be relevant. Reviewers: RKSimon, rnk, kparzysz, javed.absar Subscribers: sdardis, nemanjai, hiraditya, atanasyan, llvm-commits Differential Revision: https://reviews.llvm.org/D49200 llvm-svn: 344142
* [Hexagon] Fix extracting subvectors of non-HVX vNi1Krzysztof Parzyszek2018-10-021-0/+28
| | | | | | Patch by Brendon Cahoon. llvm-svn: 343596
* [Hexagon] Remove incorrect pattern for swizKrzysztof Parzyszek2018-10-011-51/+0
| | | | | | | | | | | | The pattern had a couple of problems: - It was checking for loads of bytes in the reverse order to what it should have been looking for. - It would replace loads of bytes with a load of a word without making sure that the alignment was correct. Thanks to Eli Friedman for pointing it out. llvm-svn: 343514
* [MachineVerifier] Relax checkLivenessAtDef regarding dead subreg defsBjorn Pettersson2018-09-201-0/+74
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Consider an instruction that has multiple defs of the same vreg, but defining different subregs: %7.sub1:rc, dead %7.sub2:rc = inst Calling checkLivenessAtDef for the live interval associated with %7 incorrectly reported "live range continues after a dead def". The live range for %7 has a dead def at the slot index for "inst" even if the live range continues (given that there are later uses of %7.sub1). This patch adjusts MachineVerifier::checkLivenessAtDef to allow dead subregister definitions, unless we are checking a subrange (when tracking subregister liveness). A limitation is that we do not detect the situation when the live range continues past an instruction that defines the full virtual register by multiple dead subreg defines. I also removed some dead code related to physical register in checkLivenessAtDef. Wwe only call that method for virtual registers, so I added an assertion instead. Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D52237 llvm-svn: 342618
* Copy utilities updated and added for MI flagsMichael Berg2018-09-191-1/+1
| | | | | | | | | | | | | | Summary: This patch adds a GlobalIsel copy utility into MI for flags and updates the instruction emitter for the SDAG path. Some tests show new behavior and I added one for GlobalIsel which mirrors an SDAG test for handling nsw/nuw. Reviewers: spatel, wristow, arsenm Reviewed By: arsenm Subscribers: wdng Differential Revision: https://reviews.llvm.org/D52006 llvm-svn: 342576
* [PostRASink] Make sure to remove subregisters from live-ins as wellKrzysztof Parzyszek2018-09-181-0/+33
| | | | llvm-svn: 342492
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+121
| | | | | | | | Shufflevector instructions in LLVM IR that extract a subset of elements of a longer input into a shorter vector can be done using VECTOR_SHUFFLEs. This will avoid expanding them into constly extracts and inserts. llvm-svn: 342091
* [Hexagon] [Test] Remove undef and infinite loop from testRoman Lebedev2018-09-111-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | Summary: The undef and the infinite loop at the end cause this test to be translated unpredictably. In particular, the checked-for `mpy` disappears under certain legal optimizations (e.g. the one in D50222). Since the use of these constructs is not relevant to the behavior tested, according to the header comment, this change, suggested by @kparzysz, eliminates them. Was initially committed in r341046, but was reverted. Patch by: hermord (Dmytro Shynkevych)! Reviewers: kparzysz Reviewed By: kparzysz Subscribers: lebedev.ri, llvm-commits, kparzysz Differential Revision: https://reviews.llvm.org/D50944 llvm-svn: 341943
* Add support for getRegisterByName.Sid Manning2018-09-071-0/+13
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341658
* [Hexagon] Don't packetize new-value stores with any other storesKrzysztof Parzyszek2018-09-041-0/+25
| | | | llvm-svn: 341409
* Revert [Hexagon] Add support for getRegisterByName.Sid Manning2018-09-031-23/+0
| | | | | | Support required to build the Hexagon Linux kernel. llvm-svn: 341331
* [Hexagon] Add support for getRegisterByName.Sid Manning2018-08-311-0/+23
| | | | | | | | Support required to build the Hexagon Linux kernel. Differential Revision: https://reviews.llvm.org/D51363 llvm-svn: 341238
* [Hexagon] Check validity of register class when generating bitsplitKrzysztof Parzyszek2018-08-301-0/+40
| | | | llvm-svn: 341137
* Revert "[Hexagon][Test] Remove undef and infinite loop from test"Roman Lebedev2018-08-301-3/+3
| | | | | | | | | | | | | | | Bots are unhappy: /Users/buildslave/jenkins/workspace/clang-stage1-cmake-RA-incremental/llvm/test/CodeGen/Hexagon/swp-const-tc2.ll:10:14: error: CHECK-NOT: excluded string found in input ; CHECK-NOT: = mpy ^ <stdin>:22:6: note: found here r5 += mpyi(r2,r3) ^~~~~ This reverts commit r341046. llvm-svn: 341049
* [Hexagon][Test] Remove undef and infinite loop from testRoman Lebedev2018-08-301-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Summary: As suggested in D50222, this has been refactored into a separate patch. The undef and the infinite loop at the end cause this test to be translated unpredictably. In particular, the checked-for `mpy` disappears under certain legal optimizations (e.g. the one in D50222). Since the use of these constructs is not relevant to the behavior tested, according to the header comment, this change, suggested by @kparzysz, eliminates them. Patch by: hermord (Dmytro Shynkevych)! Reviewers: kparzysz Reviewed By: kparzysz Subscribers: llvm-commits, kparzysz Differential Revision: https://reviews.llvm.org/D50944 llvm-svn: 341046
* [Pipeliner] Fix incorrect phi values in the epilog and kernelBrendon Cahoon2018-08-271-0/+33
| | | | | | | | | | | | | | | | | | | The code that generates the loop definition operand for phis in the epilog and kernel is incorrect in some cases. In the kernel, when a phi refers to another phi, the code that updates PhiOp2 needs to include the stage difference between the two phis. In the epilog, the check for using the loop definition instead of the phi definition uses the StageDiffAdj value (the difference between the phi stage and the loop definition stage), but the adjustment is not needed to determine if the current stage contains an iteration with the loop definition. Differential Revision: https://reviews.llvm.org/D51167 llvm-svn: 340782
* [CodeGen] Set FrameSetup/FrameDestroy on BUNDLE instructionsBjorn Pettersson2018-08-251-0/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: If any of the bundled instructions are marked as FrameSetup or FrameDestroy, then that property is set on the BUNDLE instruction as well. As long as the scheduler/packetizer aren't mixing prologue/epilogue instructions (i.e. all the bundled instructions have the same property) then this simply gives the bundle the correct property (so when using a bundle iterator in late passes a bundle will be correctly identified as FrameSetup/FrameDestroy). When for example bundling a mix of FrameSetup instructions with non-FrameSetup instructions it could be discussed if the bundle should have the property or not. The choice here has been to set these properties on the BUNDLE instruction if any of the bundled instructions have the property set. Reviewers: #debug-info, kparzysz Reviewed By: kparzysz Subscribers: vsk, thegameg, llvm-commits Differential Revision: https://reviews.llvm.org/D50637 llvm-svn: 340680
* [Hexagon] Enable interleaving in loop vectorizerKrzysztof Parzyszek2018-08-221-0/+52
| | | | llvm-svn: 340447
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