[Hexagon] Add instruction definitions for Hexagon V66

llvm-svn: 348411

2 files changed, 34 insertions, 0 deletions

diff --git a/llvm/test/CodeGen/Hexagon/dfp.ll b/llvm/test/CodeGen/Hexagon/dfp.ll
new file mode 100644
index 00000000000..e4fe10bad0b
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/dfp.ll
@@ -0,0 +1,19 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+
+; CHECK-LABEL: df_add:
+; CHECK: dfadd
+define double @df_add(double %x, double %y) local_unnamed_addr #0 {
+entry:
+  %add = fadd double %x, %y
+  ret double %add
+}
+
+; CHECK-LABEL: df_sub:
+; CHECK: dfsub
+define double @df_sub(double %x, double %y) local_unnamed_addr #0 {
+entry:
+  %sub = fsub double %x, %y
+  ret double %sub
+}
+
+attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv66" }
diff --git a/llvm/test/CodeGen/Hexagon/mnaci_v66.ll b/llvm/test/CodeGen/Hexagon/mnaci_v66.ll
new file mode 100644
index 00000000000..63f3788fe56
--- /dev/null
+++ b/llvm/test/CodeGen/Hexagon/mnaci_v66.ll
@@ -0,0 +1,15 @@
+; RUN: llc -march=hexagon < %s | FileCheck %s
+; This test validates the generation of v66 only instruction M2_mnaci
+; CHECK: r{{[0-9]+}} -= mpyi(r{{[0-9]+}},r{{[0-9]+}})
+
+target triple = "hexagon-unknown--elf"
+
+; Function Attrs: norecurse nounwind readnone
+define i32 @_Z4testiii(i32 %a, i32 %b, i32 %c) #0 {
+entry:
+  %mul = mul nsw i32 %c, %b
+  %sub = sub nsw i32 %a, %mul
+  ret i32 %sub
+}
+
+attributes #0 = { norecurse nounwind readnone "target-cpu"="hexagonv66" "target-features"="-hvx,-long-calls" }