| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [Hexagon] Generate vector min/max for HVX | Krzysztof Parzyszek | 2019-08-15 | 1 | -90/+90 |
| | | | | | llvm-svn: 369014 | ||||
| * | [Hexagon] Add patterns for accumulating HVX compares | Krzysztof Parzyszek | 2018-05-22 | 1 | -0/+297 |
| | | | | | llvm-svn: 333009 | ||||
| * | [Hexagon] Handle lowering of SETCC via setCondCodeAction | Krzysztof Parzyszek | 2018-02-06 | 1 | -30/+15 |
| | | | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348 | ||||
| * | [Hexagon] Generate HVX code for comparisons and selects | Krzysztof Parzyszek | 2017-12-14 | 1 | -0/+294 |
| llvm-svn: 320744 | |||||
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index : bcm5719-llvm | |
| Project Ortega BCM5719 LLVM | Raptor Computing Systems |
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