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* [MVT] Add v256i1 to MachineValueTypeKrzysztof Parzyszek2019-09-201-0/+15
| | | | | | This type can show up when lowering some HVX vector code on Hexagon. llvm-svn: 372403
* [Hexagon] Generate vector min/max for HVXKrzysztof Parzyszek2019-08-154-180/+868
| | | | llvm-svn: 369014
* [Hexagon] Remove fcmp undef from reduced testsSimon Pilgrim2019-03-291-2/+2
| | | | | | | | Pre-commit for D60006 (Add fcmp UNDEF handling to SelectionDAG::FoldSetCC) Approved by @kparzysz (Krzysztof Parzyszek) llvm-svn: 357301
* [Hexagon] Remove icmp undef from reduced testsSimon Pilgrim2019-03-151-1/+1
| | | | | | | | Pre-commit for D59363 (Add icmp UNDEF handling to SelectionDAG::FoldSetCC) Approved by @kparzysz (Krzysztof Parzyszek) llvm-svn: 356267
* [Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTENDKrzysztof Parzyszek2019-02-201-0/+16
| | | | llvm-svn: 354473
* [DAGCombiner] allow hoisting vector bitwise logic ahead of truncatesSanjay Patel2018-12-162-18/+18
| | | | | | | | | | | | | | | | | | The transform performs a bitwise logic op in a wider type followed by truncate when both inputs are truncated from the same source type: logic_op (truncate x), (truncate y) --> truncate (logic_op x, y) There are a bunch of other checks that should prevent doing this when it might be harmful. We already do this transform for scalars in this spot. The vector limitation was shared with a check for the case when the operands are extended. I'm not sure if that limit is needed either, but that would be a separate patch. Differential Revision: https://reviews.llvm.org/D55448 llvm-svn: 349303
* [Hexagon] make test immune to scalarization improvements; NFCSanjay Patel2018-12-141-3/+3
| | | | llvm-svn: 349163
* [Hexagon] make test immune to improvements in undef simplificationSanjay Patel2018-11-191-2/+2
| | | | llvm-svn: 347218
* DAG combiner: fold (select, C, X, undef) -> XStanislav Mekhanoshin2018-11-161-1/+1
| | | | | | Differential Revision: https://reviews.llvm.org/D54646 llvm-svn: 347110
* [Hexagon] Use shuffles when lowering "gather" shufflevectorsKrzysztof Parzyszek2018-09-121-0/+121
| | | | | | | | Shufflevector instructions in LLVM IR that extract a subset of elements of a longer input into a shorter vector can be done using VECTOR_SHUFFLEs. This will avoid expanding them into constly extracts and inserts. llvm-svn: 342091
* [Hexagon] Enable interleaving in loop vectorizerKrzysztof Parzyszek2018-08-221-0/+52
| | | | llvm-svn: 340447
* [Hexagon] Simplify CFG after atomic expansionKrzysztof Parzyszek2018-08-0217-58/+68
| | | | | | | | | | This will remove suboptimal branching from the generated ll/sc loops. The extra simplification pass affects a lot of testcases, which have been modified to accommodate this change: either by modifying the test to become immune to the CFG simplification, or (less preferablt) by adding option -hexagon-initial-cfg-clenaup=0. llvm-svn: 338774
* [Hexagon] Make floating point operations expensive for vectorizationKrzysztof Parzyszek2018-06-121-0/+91
| | | | llvm-svn: 334508
* [Hexagon] Implement vector-pair zero as V6_vsubw_dvKrzysztof Parzyszek2018-06-061-0/+41
| | | | llvm-svn: 334123
* [Hexagon] Split CTPOP of vector pairsKrzysztof Parzyszek2018-06-061-0/+26
| | | | llvm-svn: 334109
* [Hexagon] Select HVX code for vector CTPOP, CTLZ, and CTTZKrzysztof Parzyszek2018-06-012-0/+249
| | | | llvm-svn: 333760
* [Hexagon] Use vector align-left when shift amount fits in 3 bitsKrzysztof Parzyszek2018-05-304-56/+28
| | | | | | | This saves an instruction because for align-right the shift amount would need to be put in a register first. llvm-svn: 333543
* [Hexagon] Fix packing source vectors in shufflevector selection Krzysztof Parzyszek2018-05-251-0/+12
| | | | | | | | When the shuffle mask selected a subvector of the second input vector, and aligning of the source was performed, the shuffle mask was updated incorrectly, resulting in an ICE further in the selection process. llvm-svn: 333279
* [Hexagon] Add patterns for accumulating HVX comparesKrzysztof Parzyszek2018-05-224-72/+651
| | | | llvm-svn: 333009
* [Hexagon] Mark HVX vector predicate bitwise ops as legal, add patternsKrzysztof Parzyszek2018-05-162-0/+204
| | | | llvm-svn: 332525
* [Hexagon] Add patterns for vector shift-and-accumulateKrzysztof Parzyszek2018-05-092-432/+65
| | | | llvm-svn: 331918
* [Hexagon] Improve HVX instruction selection (bitcast, vsplat)Krzysztof Parzyszek2018-04-202-0/+76
| | | | | | | | | | There was some unfortunate interaction between VSPLAT and BITCAST related to the selection of constant vectors (coming from selecting shuffles). Introduce VSPLATW that always splats a 32-bit word, and can have arbitrary result type (to avoid BITCASTs of VSPLAT). Clean up the previous selection of BITCAST/VSPLAT. llvm-svn: 330471
* [Hexagon] Use legal types when lowering CONCAT_VECTORS via BUILD_VECTORKrzysztof Parzyszek2018-04-191-0/+34
| | | | llvm-svn: 330344
* [Hexagon] Generate code for vector bswap intrinsicsKrzysztof Parzyszek2018-04-191-0/+45
| | | | llvm-svn: 330333
* [Hexagon] Implement TTI::shouldMaximizeVectorBandwidthKrzysztof Parzyszek2018-03-271-0/+47
| | | | llvm-svn: 328648
* [Hexagon] Add heuristic to exclude critical path cost for schedulingKrzysztof Parzyszek2018-03-201-2/+1
| | | | | | Patch by Brendon Cahoon. llvm-svn: 328022
* [Hexagon] Improve scheduling based on register pressureKrzysztof Parzyszek2018-03-201-1/+2
| | | | | | Patch by Brendon Cahoon. llvm-svn: 327975
* [Hexagon] Ignore indexed loads when handling unaligned loadsKrzysztof Parzyszek2018-03-081-0/+67
| | | | llvm-svn: 327037
* [Hexagon] Rewrite non-HVX unaligned loads as pairs of aligned onesKrzysztof Parzyszek2018-03-071-1/+1
| | | | | | | | | This is a follow-up to r325169, this time for all types, not just HVX vector types. Disable this by default, since it's not always safe. llvm-svn: 326915
* [Hexagon] Generate valignb for shifting shuffles (instead of vdelta)Krzysztof Parzyszek2018-03-022-0/+2548
| | | | llvm-svn: 326627
* [Hexagon] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-211-2/+2
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Krzysztof Parzyszek llvm-svn: 325697
* [Hexagon] Split HVX vector pair loads/stores, expand unaligned loadsKrzysztof Parzyszek2018-02-141-0/+26
| | | | llvm-svn: 325169
* [Hexagon] Add code to select QTRUE and QFALSEKrzysztof Parzyszek2018-02-091-0/+29
| | | | | | Fixes http://llvm.org/PR36320. llvm-svn: 324763
* [Hexagon] Lower concat of more than 2 vectors into build_vectorKrzysztof Parzyszek2018-02-061-0/+35
| | | | llvm-svn: 324391
* [Hexagon] Split HVX operations on vector pairsKrzysztof Parzyszek2018-02-063-0/+77
| | | | | | | | Vector pairs are legal types, but not every operation can work on pairs. For those operations that are legal for single vectors, generate a concat of their results on pair halves. llvm-svn: 324350
* [Hexagon] Handle lowering of SETCC via setCondCodeActionKrzysztof Parzyszek2018-02-062-60/+30
| | | | | | | | | | It was expanded directly into instructions earlier. That was to avoid loads from a constant pool for a vector negation: "xor x, splat(i1 -1)". Implement ISD opcodes QTRUE and QFALSE to denote logical vectors of all true and all false values, and handle setcc with negations through selection patterns. llvm-svn: 324348
* [Hexagon] Use V6_vmpyih for halfword multiplicationKrzysztof Parzyszek2018-02-051-4/+2
| | | | | | | Unlike V6_vmpyhv, it produces the result in the exact form that is expected without the need for a shuffle. llvm-svn: 324241
* [Hexagon] Implement HVX codegen for vector shiftsKrzysztof Parzyszek2018-01-313-1/+609
| | | | llvm-svn: 323914
* [Hexagon] Handle ANY_EXTEND_VECTOR_INREG in loweringKrzysztof Parzyszek2018-01-311-0/+20
| | | | llvm-svn: 323912
* [Hexagon] Handle SETCC on vector pairs in loweringKrzysztof Parzyszek2018-01-311-0/+29
| | | | llvm-svn: 323911
* [Hexagon] Handle BUILD_VECTOR from undef values in buildHvxVectorRegKrzysztof Parzyszek2018-01-311-0/+39
| | | | llvm-svn: 323889
* [Hexagon] Only process bitcasts of vsplats when selecting const vectorsKrzysztof Parzyszek2018-01-311-0/+37
| | | | | | | | Selecting of constant HVX vectors involves some "manual processing", which mishandled an unrelated BITCAST operation causing a selection error. llvm-svn: 323887
* [Hexagon] Generate constant splats instead of loads from constant poolKrzysztof Parzyszek2018-01-261-0/+12
| | | | llvm-svn: 323568
* [Hexagon] Run late copy propagation and dead code elimination passesKrzysztof Parzyszek2018-01-244-16/+20
| | | | llvm-svn: 323346
* [Hexagon] Add patterns for sext_inreg of HVX vector typesKrzysztof Parzyszek2018-01-231-0/+54
| | | | llvm-svn: 323250
* [Hexagon] Implement basic vector operations on vectors vNi1Krzysztof Parzyszek2018-01-231-0/+20
| | | | | | | | | | | In addition to that, make sure that there are no boolean vector types that are associated with multiple register classes. Specifically, remove v32i1 and v64i1 from integer register classes. These types will correspond to results of vector comparisons, and as such should belong to the vector predicate class. Having them in scalar registers as well makes legalization ambiguous. llvm-svn: 323229
* [Hexagon] Cast elements to correct type when creating constant vectorKrzysztof Parzyszek2018-01-111-0/+12
| | | | llvm-svn: 322301
* [Hexagon] Even simpler patterns for sign- and zero-extending HVX vectorsKrzysztof Parzyszek2018-01-053-50/+18
| | | | | | Recommit r321897 with updated testcases. llvm-svn: 321908
* Revert r321894: it requires a part of another commit that is not ready yetKrzysztof Parzyszek2018-01-051-54/+0
| | | | | | | Commit message: [Hexagon] Add patterns for sext_inreg of HVX vector types llvm-svn: 321904
* [Hexagon] Add patterns for truncating HVX vector typesKrzysztof Parzyszek2018-01-051-0/+18
| | | | | | Only non-bool vectors. llvm-svn: 321895
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