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* [AVR] Fix incorrect source regclass of LDWRdPtrJim Lin2019-06-032-38/+3
| | | | | | | | | | | | | | | | | | Summary: LDWRdPtr would be expanded to ld+ldd. ldd only accepts the pointer register is Y or Z. So the register class of pointer of LDWRdPtr should be PTRDISPREGS instead of PTRREGS. Reviewers: dylanmckay Reviewed By: dylanmckay Subscribers: dylanmckay, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62300 llvm-svn: 362351
* [AVR] Fix codegen bug in 16-bit loadsDylan McKay2019-01-202-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | Prior to this patch, the AVR::LDWRdPtr instruction was always lowered to instructions of this pattern: ld $GPR8, [PTR:XYZ]+ ld $GPR8, [PTR]+1 This has a problem; the [PTR] is incremented in-place once, but never decremented. Future uses of the same pointer will use the now clobbered value, leading to the pointer being incorrect by an offset of one. This patch modifies the expansion code of the LDWRdPtr pseudo instruction so that the pointer variable is not silently clobbered in future uses in the same live range. Bug first reported by Keshav Kini. Patch by Kaushik Phatak. llvm-svn: 351673
* Revert "[AVR] Fix codegen bug in 16-bit loads"Dylan McKay2019-01-202-4/+4
| | | | | | | | | | | This reverts commit r351544. In that commit, I had mistakenly misattributed the issue submitter as the patch author, Kaushik Phatak. The patch will be recommitted immediately with the correct attribution. llvm-svn: 351672
* [AVR] Fix codegen bug in 16-bit loadsDylan McKay2019-01-182-4/+4
| | | | | | | | | | | | | | | | | | | | | | Prior to this patch, the AVR::LDWRdPtr instruction was always lowered to instructions of this pattern: ld $GPR8, [PTR:XYZ]+ ld $GPR8, [PTR]+1 This has a problem; the [PTR] is incremented in-place once, but never decremented. Future uses of the same pointer will use the now clobbered value, leading to the pointer being incorrect by an offset of one. This patch modifies the expansion code of the LDWRdPtr pseudo instruction so that the pointer variable is not silently clobbered in future uses in the same live range. Patch by Keshav Kini. llvm-svn: 351544
* [AVR] Disallow the LDDWRdPtrQ instruction with Z as the destinationDylan McKay2018-11-052-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is an AVR-specific workaround for a limitation of the register allocator that only exposes itself on targets with high register contention like AVR, which only has three pointer registers. The three pointer registers are X, Y, and Z. In most nontrivial functions, Y is reserved for the frame pointer, as per the calling convention. This leaves X and Z. Some instructions, such as LPM ("load program memory"), are only defined for the Z register. Sometimes this just leaves X. When the backend generates a LDDWRdPtrQ instruction with Z as the destination pointer, it usually trips up the register allocator with this error message: LLVM ERROR: ran out of registers during register allocation This patch is a hacky workaround. We ban the LDDWRdPtrQ instruction from ever using the Z register as an operand. This gives the register allocator a bit more space to allocate, fixing the regalloc exhaustion error. Here is a description from the patch author Peter Nimmervoll As far as I understand the problem occurs when LDDWRdPtrQ uses the ptrdispregs register class as target register. This should work, but the allocator can't deal with this for some reason. So from my testing, it seams like (and I might be totally wrong on this) the allocator reserves the Z register for the ICALL instruction and then the register class ptrdispregs only has 1 register left and we can't use Y for source and destination. Removing the Z register from DREGS fixes the problem but removing Y register does not. More information about the bug can be found on the avr-rust issue tracker at https://github.com/avr-rust/rust/issues/37. A bug has raised to track the removal of this workaround and a proper fix; PR39553 at https://bugs.llvm.org/show_bug.cgi?id=39553. Patch by Peter Nimmervoll llvm-svn: 346114
* [AVR] Redefine the 'LSL' instruction as an alias of 'ADD'Dylan McKay2018-09-013-3/+3
| | | | | | The 'LSL Rd' instruction is equivalent to 'ADD Rd, Rd'. llvm-svn: 341278
* [AVR] Define the ROL instruction as an alias of ADCDylan McKay2018-09-011-1/+1
| | | | | | | | | The 'rol Rd' instruction is equivalent to 'adc Rd'. This caused compile warnings from tablegen because of conflicting bits shared between each instruction. llvm-svn: 341275
* [AVR] Fix the testsuite after '%' changed to '$' in MIRDylan McKay2018-02-0838-108/+108
| | | | llvm-svn: 324583
* [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X`Dylan McKay2017-10-044-8/+8
| | | | | | Patch by Gergo Erdi. llvm-svn: 314896
* [AVR] Fix test errors due to tied operands not matchingDylan McKay2017-07-095-7/+7
| | | | | | Broken due to r307259. llvm-svn: 307503
* [AVR] Support the LDWRdPtr instruction with the same Src+Dst registerDylan McKay2017-04-253-35/+64
| | | | llvm-svn: 301313
* MIRTests: Remove unnecessary 2>&1 redirectionMatthias Braun2017-02-2237-37/+37
| | | | | | | llc mir output goes to stdout nowadays, so the 2>&1 is not necessary anymore for most tests. llvm-svn: 295859
* [AVR] Marm MIR test functions as tracking liveness informationDylan McKay2017-02-053-2/+5
| | | | | | This fixes an assertion error that broke three tests. llvm-svn: 294140
* [AVR] Explicitly set the target in all CodeGen testsDylan McKay2016-12-103-3/+3
| | | | | | This seems to have caused failures on the buildbot. llvm-svn: 289324
* [AVR] Use the register scavenger when expanding 'LDDW' instructionsDylan McKay2016-12-101-12/+13
| | | | | | | | | | | | Summary: This gets rid of the hardcoded 'r0' that was used previously. Reviewers: asl Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D27567 llvm-svn: 289322
* [AVR] Remove a set of redundant testsDylan McKay2016-12-094-88/+0
| | | | | | This fixes the build. llvm-svn: 289201
* [AVR] Add tests for a large number of pseudo instructionsDylan McKay2016-12-0926-4/+557
| | | | | | This adds MIR tests for 24 pseudo instructions. llvm-svn: 289191
* [AVR] Add MIR tests for pseudo instruction expansionsDylan McKay2016-12-0813-0/+308
| | | | | | This adds tests for 13 pseudo instruction expansions. llvm-svn: 289039
* [AVR] Add MIR tests for a few pseudo instructionsDylan McKay2016-12-083-0/+72
| | | | llvm-svn: 289031
* [AVR] Move a pseudo expansion test into a folderDylan McKay2016-12-071-0/+33
llvm-svn: 288899
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