summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/ARM
Commit message (Collapse)AuthorAgeFilesLines
* DAG: avoid duplicated truncating for sign extended operandWeiming Zhao2016-07-292-3/+112
| | | | | | | | | | | | | | | Summary: When performing cmp for EQ/NE and the operand is sign extended, we can avoid the truncaton if the bits to be tested are no less than origianl bits. Reviewers: eli.friedman Subscribers: eli.friedman, aemerson, nemanjai, t.p.northover, llvm-commits Differential Revision: https://reviews.llvm.org/D22933 llvm-svn: 277252
* [Thumb] Emit Thumb move in both Thumb modes for struct_byval predicatesPrakhar Bahuguna2016-07-291-0/+29
| | | | | | | | | | | | | | | | | Summary: The MOV/MOVT instructions being chosen for struct_byval predicates was conditional only on Thumb2, resulting in an ARM MOV/MOVT instruction being incorrectly emitted in Thumb1 mode. This is especially apparent with v8-m.base targets. This patch ensures that Thumb instructions are emitted in both Thumb modes. Reviewers: rengolin, t.p.northover Subscribers: llvm-commits, aemerson, rengolin Differential Revision: https://reviews.llvm.org/D22865 llvm-svn: 277128
* MIRParser: Use shorter cfi identifiersMatthias Braun2016-07-261-3/+3
| | | | | | | | | | | | | | | | In an instruction like: CFI_INSTRUCTION .cfi_def_cfa ... we can drop the '.cfi_' prefix since that should be obvious by the context: CFI_INSTRUCTION def_cfa ... While being a terser and cleaner syntax this also prepares to dropping support for identifiers starting with a dot character so we can use it for expressions. Differential Revision: http://reviews.llvm.org/D22388 llvm-svn: 276785
* [ARM] Saturation instructions are DSP-onlyRenato Golin2016-07-253-10/+38
| | | | | | | | | | | The saturation instructions appeared in v6T2, with DSP extensions, but they were being accepted / generated on any, with the new introduction of the saturation detection in the back-end. This commit restricts the usage to DSP-enable only cores. Fixes PR28607. llvm-svn: 276701
* [ARM] Improve longMAC codegen testSam Parker2016-07-251-34/+85
| | | | | | | | Added thumb targets and dataflow checks to the longMAC test. Differential Revision: https://reviews.llvm.org/D22684 llvm-svn: 276629
* [ARM] Enable ISel of SMMLS for ARM and Thumb2Sam Parker2016-07-251-2/+34
| | | | | | | | Use ISelDAGToDAG to recognise the SMMLS instruction pattern. Differential Revision: https://reviews.llvm.org/D22562 llvm-svn: 276624
* [ARM] Skip inline asm memory operands in DAGToDAGISelDiana Picus2016-07-201-0/+11
| | | | | | | | | | | | | | | | | | | | | | Retry r275776 (no changes, we suspect the issue was with another commit). The current logic for handling inline asm operands in DAGToDAGISel interprets the operands by looking for constants, which should represent the flags describing the kind of operand we're dealing with (immediate, memory, register def etc). The operands representing actual data are skipped only if they are non-const, with the exception of immediate operands which are skipped explicitly when a flag describing an immediate is found. The oversight is that memory operands may be const too (e.g. for device drivers reading a fixed address), so we should explicitly skip the operand following a flag describing a memory operand. If we don't, we risk interpreting that constant as a flag, which is definitely not intended. Fixes PR26038 Differential Revision: https://reviews.llvm.org/D22103 llvm-svn: 276101
* Revert "Disable this-return argument forwarding on ARM/AArch64"David Majnemer2016-07-202-4/+4
| | | | | | | | | Inference of the 'returned' attribute was fixed in r276008, lets try turning the backend support back on. This reverts commit r275677. llvm-svn: 276081
* [ARM] Refactor Thumb2 Mul and Mla instr descsSam Parker2016-07-191-4/+26
| | | | | | | | | | | Recommitting after r274347 was reverted. This patch introduces some classes to refactor the 3 and 4 register Thumb2 multiplication instruction descriptions, plus improved tests for some of those instructions. Differential Revision: https://reviews.llvm.org/D21929 llvm-svn: 275979
* Revert "[ARM] Skip inline asm memory operands in DAGToDAGISel"Vitaly Buka2016-07-181-11/+0
| | | | | | | | Breaks asan, see https://reviews.llvm.org/D22103 This reverts commit r275776. llvm-svn: 275890
* Revert "[ARM] Update test to use CHECK-LABEL. NFCI."Vitaly Buka2016-07-181-8/+6
| | | | | | | | Breaks asan, see https://reviews.llvm.org/D22103 This reverts commit r275777. llvm-svn: 275889
* CodeGenPrep: use correct function to determine Global's alignment.Tim Northover2016-07-181-0/+9
| | | | | | | | | Elsewhere (particularly computeKnownBits) we assume that a global will be aligned to the value returned by Value::getPointerAlignment. This is used to boost the alignment on memcpy/memset, so any target-specific request can only increase that value. llvm-svn: 275866
* [ARM] Update test to use CHECK-LABEL. NFCI.Diana Picus2016-07-181-6/+8
| | | | llvm-svn: 275777
* [ARM] Skip inline asm memory operands in DAGToDAGISelDiana Picus2016-07-181-0/+11
| | | | | | | | | | | | | | | | | | | | The current logic for handling inline asm operands in DAGToDAGISel interprets the operands by looking for constants, which should represent the flags describing the kind of operand we're dealing with (immediate, memory, register def etc). The operands representing actual data are skipped only if they are non-const, with the exception of immediate operands which are skipped explicitly when a flag describing an immediate is found. The oversight is that memory operands may be const too (e.g. for device drivers reading a fixed address), so we should explicitly skip the operand following a flag describing a memory operand. If we don't, we risk interpreting that constant as a flag, which is definitely not intended. Fixes PR26038 Differential Revision: https://reviews.llvm.org/D22103 llvm-svn: 275776
* [ARM] Honour ABI for rem under -O0 for EABI, GNUEABI, Android and MuslDiana Picus2016-07-181-12/+105
| | | | | | | | | | | | | | | | | | | | At higher optimization levels, we generate the libcall for DIVREM_Ix, which is fine: aeabi_{u|i}divmod. At -O0 we generate the one for REM_Ix, which is the default {u}mod{q|h|s|d}i3. This commit makes sure that we don't generate REM_Ix calls for ABIs that don't support them (i.e. where we need to use DIVREM_Ix instead). This is achieved by bailing out of FastISel, which can't handle non-double multi-reg returns, and letting the legalization infrastructure expand the REM_Ix calls. It also updates the divmod-eabi.ll test to run under -O0 as well, and adds some Windows checks to it to make sure we don't break things for it. Fixes PR27068 Differential Revision: https://reviews.llvm.org/D21926 llvm-svn: 275773
* Disable this-return argument forwarding on ARM/AArch64Hal Finkel2016-07-162-4/+4
| | | | | | | | | | | r275042 reverted function-attribute inference for the 'returned' attribute because the feature triggered self-hosting failures on ARM and AArch64. James Molloy determined that the this-return argument forwarding feature, which directly ties the returned input argument to the returned value, was the cause. It seems likely that this forwarding code contains, or triggers, a subtle bug. Disabling for now until we can track that down. llvm-svn: 275677
* ARM/MIR: Move test from MIR to CodeGen/ARM directoryMatthias Braun2016-07-161-0/+164
| | | | | | | | | | test/CodeGen/MIR/ARM/ARMLoadStoreDBG.mir is an actual test for the ARM load store optimization pass and not a test of the mir parser/printer. It belongs to test/CodeGen/ARM; This also updates the test to use the new -run-pass llc syntax. llvm-svn: 275662
* ExpandPostRAPseudos should transfer implicit uses, not only implicit defsMichael Kuperstein2016-07-151-0/+1
| | | | | | | | | | | | | | | | | | | Previously, we would expand: %BL<def> = COPY %DL<kill>, %EBX<imp-use,kill>, %EBX<imp-def> Into: %BL<def> = MOV8rr %DL<kill>, %EBX<imp-def> Dropping the imp-use on the floor. That confused CriticalAntiDepBreaker, which (correctly) assumes that if an instruction defs but doesn't use a register, that register is dead immediately before the instruction - while in this case, the high lanes of EBX can be very much alive. This fixes PR28560. Differential Revision: https://reviews.llvm.org/D22425 llvm-svn: 275634
* CodeGen: avoid emitting unnecessary CFISaleem Abdulrasool2016-07-151-3/+5
| | | | | | | | | | | | Remove unnecessary clutter in assembly output. When using SjLj EH, the CFI is not actually used for anything. Do not emit the CFI needlessly. The minor test adjustments are interesting. The prologue test was just overzealous matcching. The interesting case is the LSDA change. It was originally added to ensure that various compilations did not mangle the name (it explicitly checked the name!). However, subsequent cleanups made it more reliant on the CFI to find the name. Parse the generated code flow to generically find the label still. llvm-svn: 275614
* [ARM] Prefer indirect calls in minsize modeJames Molloy2016-07-151-0/+28
| | | | | | | | ... When we emit several calls to the same function in the same basic block. An indirect call uses a "BLX r0" instruction which has a 16-bit encoding. If many calls are made to the same target, this can enable significant code size reductions. llvm-svn: 275537
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
| | | | | | | | | | | | Currently the MIR framework prints all its outputs (errors and actual representation) on stderr. This patch fixes that by printing the regular output in the output specified with -o. Differential Revision: http://reviews.llvm.org/D22251 llvm-svn: 275314
* Do not expand SDIV when compiling for minimum code sizeSjoerd Meijer2016-07-081-4/+24
| | | | | | Differential Revision: http://reviews.llvm.org/D22139 llvm-svn: 274855
* Addressing post-commit comments regarding not expanding UDIV;Sjoerd Meijer2016-07-081-1/+1
| | | | | | we don't expand only when compiling for minimum code size. llvm-svn: 274847
* Code size optimisation: don't expand a div to a mul and and a shift sequence.Sjoerd Meijer2016-07-081-0/+25
| | | | | | | | | As a result, the urem instruction will not be expanded to a sequence of umull, lsrs, muls and sub instructions, but just a call to __aeabi_uidivmod. Differential Revision: http://reviews.llvm.org/D22131 llvm-svn: 274843
* ARM: support high registers in __builtin_longjmp on WoASaleem Abdulrasool2016-07-081-5/+3
| | | | | | | | | | Windows on ARM uses a pure thumb-2 environment. This means that it can select a high register when doing a __builtin_longjmp. We would use a tLDRi which would truncate the register to a low register. Use a t2LDRi12 to get the full register file access. Tweak the code to just load into PC, as that is an interworking branch on all supported cores anyways. llvm-svn: 274815
* [ARM] Do not test for CPUs, use SubtargetFeatures. Also remove 2 flags.Diana Picus2016-07-061-1/+1
| | | | | | | | | | | | | | | This is a follow-up for r273544. The end goal is to get rid of the isSwift / isCortexXY / isWhatever methods. This commit also removes two command-line flags that weren't used in any of the tests: widen-vmovs and swift-partial-update-clearance. The former may be easily replaced with the mattr mechanism, but the latter may not (as it is a subtarget property, and not a proper feature). Differential Revision: http://reviews.llvm.org/D21797 llvm-svn: 274620
* ARM: fix `-mlong-calls` for WoASaleem Abdulrasool2016-07-051-1/+1
| | | | | | | | | Not all code-paths set the relocation model to static for Windows. This currently breaks on Windows ARM with `-mlong-calls` when built with clang. Loosen the assertion to what it was previously. We would ideally ensure that all the configuration sets Windows to static relocation model. llvm-svn: 274570
* NFC. Fix popular typo in comment 'deferencing' --> 'dereferencing'.Nick Lewycky2016-06-281-1/+1
| | | | | | Bonus changes, * placement in X86ISelLowering and 'exerce' -> 'exercise' in test. llvm-svn: 273984
* Add support for musl-libc on ARM Linux.Rafael Espindola2016-06-246-0/+32
| | | | | | Patch by Lei Zhang! llvm-svn: 273726
* [ARM] Use aapcs_vfp for ___truncdfhf2 on v7k.Ahmed Bougacha2016-06-241-0/+9
| | | | | | | r215348 overrode the f16 libcalls to be soft-float, but v7k uses the default (hard-float) calling convention. llvm-svn: 273631
* [ARM] Lower (select_cc k k (select_cc ~k ~k x)) into (SSAT l_k x)Pablo Barrio2016-06-231-0/+215
| | | | | | | | | | | | | | | | | Summary: SSAT saturates an integer, making sure that its value lies within an interval [-k, k]. Since the constant is given to SSAT as the number of bytes set to one, k + 1 must be a power of 2, otherwise the optimization is not possible. Also, the select_cc must use < and > respectively so that they define an interval. Reviewers: mcrosier, jmolloy, rengolin Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D21372 llvm-svn: 273581
* [arm+x86] Make GNU variants behave like GNU w.r.t combining sin+cos into sincos.Daniel Sanders2016-06-211-0/+18
| | | | | | | | | | | | | | | | Summary: canCombineSinCosLibcall() would previously combine sin+cos into sincos for GNUX32/GNUEABI/GNUEABIHF regardless of whether UnsafeFPMath were set or not. However, GNU would only combine them for UnsafeFPMath because sincos does not set errno like sin and cos do. It seems likely that this is an oversight. Reviewers: t.p.northover Subscribers: t.p.northover, aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D21431 llvm-svn: 273259
* Use shouldAssumeDSOLocal.Rafael Espindola2016-06-201-0/+19
| | | | | | With this ARM fast isel knows that PIE variable are not preemptable. llvm-svn: 273169
* [ARM] Enable isel of UMAALSam Parker2016-06-201-0/+29
| | | | | | | | | | TargetLowering and DAGToDAG are used to combine ADDC, ADDE and UMLAL dags into UMAAL. Selection is split into the two phases because it is easier to match the two patterns at those different times. Differential Revision: http://http://reviews.llvm.org/D21461 llvm-svn: 273165
* ARM: take account of possible bundle when erasing an instruction.Tim Northover2016-06-171-0/+16
| | | | | | | Fortunately this appears to be the only ARM-specific pass that runs while bundles might be in play, so no other cases need modifying. llvm-svn: 273029
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-171-0/+8
| | | | | | | | | | | | | | | | | | | Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
* Don't print (PLT) on arm.Rafael Espindola2016-06-164-23/+23
| | | | | | | | | The R_ARM_PLT32 relocation is deprecated and is not produced by MC. This means that the code being deleted is dead from the .o point of view and was making the .s more confusing. llvm-svn: 272909
* Reverting r272778 because there's an assertionRanjeet Singh2016-06-151-8/+0
| | | | | | failure when running the test CodeGen/ARM/intrinsics-coprocessor.ll llvm-svn: 272791
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-151-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D21178 llvm-svn: 272778
* [SelectionDAG] Remove exit-on-error flag from test (PR27765)Diana Picus2016-06-141-2/+3
| | | | | | | | | | | | | | | | The exit-on-error flag in the ARM test is necessary in order to avoid an unreachable in the DAGTypeLegalizer, when trying to expand a physical register. We can also avoid this situation by introducing a bitcast early on, where the invalid scalar-to-vector conversion is detected. We also add a test for PowerPC, which goes through a similar code path in the SelectionDAGBuilder. Fixes PR27765. Differential Revision: http://reviews.llvm.org/D21061 llvm-svn: 272644
* [ARM] Reverting r272544 because clang patch needsRanjeet Singh2016-06-131-8/+0
| | | | | | | to go in as soon as llvm patch has gone in because tests will start breaking in Clang. llvm-svn: 272546
* [ARM] Add mrrc/mrrc2 co-processor intrinsicsRanjeet Singh2016-06-131-0/+8
| | | | | | | | | | | | | MRRC/MRRC2 instruction writes to two registers. The intrinsic definition returns a single uint64_t to represent the write, this is a compact way of representing a write to two 32 bit registers, the alternative might have been two return a struct of 2 uint32_t's but this isn't as nice. Differential Revision: llvm-svn: 272544
* Reapply "[MBP] Reduce code size by running tail merging in MBP.""Haicheng Wu2016-06-091-1/+1
| | | | | | | | | | | | | | | | This reapplies commit r271930, r271915, r271923. They hit a bug in Thumb which is fixed in r272258 now. The original message: The code layout that TailMerging (inside BranchFolding) works on is not the final layout optimized based on the branch probability. Generally, after BlockPlacement, many new merging opportunities emerge. This patch calls Tail Merging after MBP and calls MBP again if Tail Merging merges anything. llvm-svn: 272267
* [ARM] MSR instructions implicitly set CPSROliver Stannard2016-06-081-0/+55
| | | | | | | | | | | | | | | The MSR instructions can write to the CPSR, but we did not model this fact, so we could emit them in the middle of IT blocks, changing the condition flags for later instructions in the block. The tests use two calls to llvm.write_register.i32 because it is valid to use these instructions at the end of an IT block, which if conversion does do in some cases. With two calls, the first clobbers the flags, so a branch has to be used to make the second one conditional. Differential Revision: http://reviews.llvm.org/D21139 llvm-svn: 272154
* Revert "[MBP] Reduce code size by running tail merging in MBP."Haicheng Wu2016-06-071-1/+1
| | | | | | | This reverts commit r271930, r271915, r271923. They break a thumb selfhosting bot. llvm-svn: 272017
* [ARM] Shrink post-indexed LDR and STR to LDM/STMJames Molloy2016-06-071-0/+52
| | | | | | | | | | | | | | A Thumb-2 post-indexed LDR instruction such as: ldr.w r0, [r1], #4 Can be rewritten as: ldm.n r1!, {r0} LDMs can be more expensive than LDRs on some cores, so this has been enabled only in minsize mode. llvm-svn: 272002
* [ARM] Transform LDMs into writeback form to save code sizeJames Molloy2016-06-071-0/+21
| | | | | | | | | | | | | | If we have an LDM that uses only low registers and doesn't write to its base register: ldm.w r0, {r1, r2, r3} And that base register is dead after the LDM, then we can convert it to writeback form and use a narrow encoding: ldm.n r0!, {r1, r2, r3} Obviously, this introduces a new register write and so can cause WAW hazards, so I've enabled it only in minsize mode. This is a code size trick that ARM Compiler 5 ("armcc") does that we don't. llvm-svn: 272000
* ARM: correct TLS access on WoASaleem Abdulrasool2016-06-071-15/+29
| | | | | | | | | | | | TLS access requires an offset from the TLS index. The index itself is the section-relative distance of the symbol. For ARM, the relevant relocation (IMAGE_REL_ARM_SECREL) is applied as a constant. This means that the value may not be an immediate and must be lowered into a constant pool. This offset will not be base relocated. We were previously emitting the actual address of the symbol which would be base relocated and would therefore be the vaue offset by the ImageBase + TLS Offset. llvm-svn: 271974
* [MBP] Reduce code size by running tail merging in MBP.Haicheng Wu2016-06-061-1/+1
| | | | | | | | | | | | | The code layout that TailMerging (inside BranchFolding) works on is not the final layout optimized based on the branch probability. Generally, after BlockPlacement, many new merging opportunities emerge. This patch calls Tail Merging after MBP and calls MBP again if Tail Merging merges anything. Differential Revision: http://reviews.llvm.org/D20276 llvm-svn: 271925
* Code size optimisation: do not inline memcpy if this expansion resultsSjoerd Meijer2016-06-031-0/+33
| | | | | | | | in more instructions than the libary call. Differential Revision: http://reviews.llvm.org/D20958 llvm-svn: 271678
OpenPOWER on IntegriCloud