diff options
| author | Ranjeet Singh <Ranjeet.Singh@arm.com> | 2016-06-15 11:32:24 +0000 |
|---|---|---|
| committer | Ranjeet Singh <Ranjeet.Singh@arm.com> | 2016-06-15 11:32:24 +0000 |
| commit | 351364fe763f65ca504cb59deff29d3aee85ead8 (patch) | |
| tree | 0ef276afc7555ced637e08643bb14134b1b03d98 /llvm/test/CodeGen/ARM | |
| parent | 8d5ad5bdf27e27a1c3c86b35908bbf34c002e48e (diff) | |
| download | bcm5719-llvm-351364fe763f65ca504cb59deff29d3aee85ead8.tar.gz bcm5719-llvm-351364fe763f65ca504cb59deff29d3aee85ead8.zip | |
[ARM] Add support for mrrc/mrrc2 intrinsics.
Differential Revision: http://reviews.llvm.org/D21178
llvm-svn: 272778
Diffstat (limited to 'llvm/test/CodeGen/ARM')
| -rw-r--r-- | llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll index ccaf5c29fad..8fea49b39fb 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll @@ -35,6 +35,10 @@ entry: tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind ; CHECK: stc2l p7, c3, [r{{[0-9]+}}] tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind + ; CHECK: mrrc p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 + %2 = tail call { i32, i32 } @llvm.arm.mrrc(i32 1, i32 2, i32 3) nounwind + ; CHECK: mrrc2 p1, #2, r{{[0-9]+}}, r{{[0-9]+}}, c3 + %3 = tail call { i32, i32 } @llvm.arm.mrrc2(i32 1, i32 2, i32 3) nounwind ret void } @@ -69,3 +73,7 @@ declare i32 @llvm.arm.mrc2(i32, i32, i32, i32, i32) nounwind declare void @llvm.arm.mcr(i32, i32, i32, i32, i32, i32) nounwind declare i32 @llvm.arm.mrc(i32, i32, i32, i32, i32) nounwind + +declare { i32, i32 } @llvm.arm.mrrc(i32, i32, i32) nounwind + +declare { i32, i32 } @llvm.arm.mrrc2(i32, i32, i32) nounwind |
