| Commit message (Expand) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | [ARM] Improve the instruction selection of vector loads. | Quentin Colombet | 2013-07-03 | 1 | -0/+24 |
| * | ARM NEON: Handle v16i8 and v8i16 reverse shuffles | Arnold Schwaighofer | 2013-02-12 | 1 | -0/+27 |
| * | ARM VLDR/VSTR instructions don't need a size suffix. | Jim Grosbach | 2011-11-14 | 1 | -3/+3 |
| * | Fix a DAG combiner assertion failure when constant folding BUILD_VECTORS. | Bob Wilson | 2011-10-18 | 1 | -0/+10 |
| * | Prevent ARM DAG Combiner from doing an AND or OR combine on an illegal vector... | Tanya Lattner | 2011-04-07 | 1 | -0/+18 |
| * | PR9139: Specify ARM/Darwin triple for vector-DAGCombine.ll test. | Bob Wilson | 2011-02-14 | 1 | -2/+2 |
| * | Add ARM-specific DAG combining to cast i64 vector element load/stores to f64. | Bob Wilson | 2010-12-21 | 1 | -0/+30 |
| * | Fix a DAGCombiner crash when folding binary vector operations with constant | Bob Wilson | 2010-12-17 | 1 | -0/+14 |
| * | Combine several vector-related DAGCombiner tests. | Bob Wilson | 2010-12-17 | 1 | -0/+63 |

