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| author | Jim Grosbach <grosbach@apple.com> | 2011-11-14 23:03:21 +0000 |
|---|---|---|
| committer | Jim Grosbach <grosbach@apple.com> | 2011-11-14 23:03:21 +0000 |
| commit | 3e2c6f380c5700d17370a4bfa998acffeed1c32d (patch) | |
| tree | 233060be861c2984ea971849474856156a3c32b4 /llvm/test/CodeGen/ARM/vector-DAGCombine.ll | |
| parent | 0201a4c2d361efa54155c482d250bdc869bd472f (diff) | |
| download | bcm5719-llvm-3e2c6f380c5700d17370a4bfa998acffeed1c32d.tar.gz bcm5719-llvm-3e2c6f380c5700d17370a4bfa998acffeed1c32d.zip | |
ARM VLDR/VSTR instructions don't need a size suffix.
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.
llvm-svn: 144583
Diffstat (limited to 'llvm/test/CodeGen/ARM/vector-DAGCombine.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/vector-DAGCombine.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll index 1a97982eb0a..a38a0feae04 100644 --- a/llvm/test/CodeGen/ARM/vector-DAGCombine.ll +++ b/llvm/test/CodeGen/ARM/vector-DAGCombine.ll @@ -80,7 +80,7 @@ declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind ; so they are not split up into i32 values. Radar 8755338. define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind { ; CHECK: i64_buildvector -; CHECK: vldr.64 +; CHECK: vldr %t0 = load i64* %ptr, align 4 %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0 store <2 x i64> %t1, <2 x i64>* %vp @@ -89,7 +89,7 @@ define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind { define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind { ; CHECK: i64_insertelement -; CHECK: vldr.64 +; CHECK: vldr %t0 = load i64* %ptr, align 4 %vec = load <2 x i64>* %vp %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0 @@ -99,7 +99,7 @@ define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind { define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind { ; CHECK: i64_extractelement -; CHECK: vstr.64 +; CHECK: vstr %vec = load <2 x i64>* %vp %t1 = extractelement <2 x i64> %vec, i32 0 store i64 %t1, i64* %ptr |
