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* [ARM] Prefer BIC over BFC in ARM mode.Eli Friedman2017-04-071-4/+4
| | | | | | | | | | | | BIC is generally faster, and it can put the output in a different register from the input. We already do this in Thumb2 mode; not sure why the equivalent fix never got applied to ARM mode. Differential Revision: https://reviews.llvm.org/D31797 llvm-svn: 299803
* AArch64 & ARM: remove undefined behaviour from some tests.Tim Northover2014-05-301-2/+2
| | | | llvm-svn: 209880
* Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier ↵Stephen Lin2013-07-131-2/+2
| | | | | | | | | | debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
* Make this test less sensitive to codegen optimizations.Dan Gohman2011-10-051-0/+1
| | | | llvm-svn: 141195
* Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor ↵Andrew Trick2011-04-131-5/+5
| | | | | | | | | | | | | | | | | | | | | latency. Additional fixes: Do something reasonable for subtargets with generic itineraries by handle node latency the same as for an empty itinerary. Now nodes default to unit latency unless an itinerary explicitly specifies a zero cycle stage or it is a TokenFactor chain. Original fixes: UnitsSharePred was a source of randomness in the scheduler: node priority depended on the queue data structure. I rewrote the recent VRegCycle heuristics to completely replace the old heuristic without any randomness. To make the ndoe latency adjustments work, I also needed to do something a little more reasonable with TokenFactor. I gave it zero latency to its consumers and always schedule it as low as possible. llvm-svn: 129421
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-1/+23
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* When splitting a VAARG, remember its alignment.Rafael Espindola2010-06-261-0/+19
This produces terrible but correct code. llvm-svn: 106952
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