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| author | Andrew Trick <atrick@apple.com> | 2011-04-13 00:38:32 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2011-04-13 00:38:32 +0000 |
| commit | b53a00d2cbc643d461ebd57e8f029f38631bfd34 (patch) | |
| tree | 0bb4300556bfe91933aaf65004de971f1ac5d721 /llvm/test/CodeGen/ARM/va_arg.ll | |
| parent | 3137d3cb499af07c021f5a12dad1cd5418dd024f (diff) | |
| download | bcm5719-llvm-b53a00d2cbc643d461ebd57e8f029f38631bfd34.tar.gz bcm5719-llvm-b53a00d2cbc643d461ebd57e8f029f38631bfd34.zip | |
Recommit r129383. PreRA scheduler heuristic fixes: VRegCycle, TokenFactor latency.
Additional fixes:
Do something reasonable for subtargets with generic
itineraries by handle node latency the same as for an empty
itinerary. Now nodes default to unit latency unless an itinerary
explicitly specifies a zero cycle stage or it is a TokenFactor chain.
Original fixes:
UnitsSharePred was a source of randomness in the scheduler: node
priority depended on the queue data structure. I rewrote the recent
VRegCycle heuristics to completely replace the old heuristic without
any randomness. To make the ndoe latency adjustments work, I also
needed to do something a little more reasonable with TokenFactor. I
gave it zero latency to its consumers and always schedule it as low as
possible.
llvm-svn: 129421
Diffstat (limited to 'llvm/test/CodeGen/ARM/va_arg.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/va_arg.ll | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/llvm/test/CodeGen/ARM/va_arg.ll b/llvm/test/CodeGen/ARM/va_arg.ll index 7cb976236dc..bb404531162 100644 --- a/llvm/test/CodeGen/ARM/va_arg.ll +++ b/llvm/test/CodeGen/ARM/va_arg.ll @@ -1,10 +1,10 @@ -; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi | FileCheck %s +; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s ; Test that we correctly align elements when using va_arg ; CHECK: test1: ; CHECK-NOT: bfc -; CHECK: add r0, r0, #7 -; CHECK: bfc r0, #0, #3 +; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 +; CHECK: bfc [[REG]], #0, #3 ; CHECK-NOT: bfc define i64 @test1(i32 %i, ...) nounwind optsize { @@ -19,8 +19,8 @@ entry: ; CHECK: test2: ; CHECK-NOT: bfc -; CHECK: add r0, r0, #7 -; CHECK: bfc r0, #0, #3 +; CHECK: add [[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7 +; CHECK: bfc [[REG]], #0, #3 ; CHECK-NOT: bfc ; CHECK: bx lr |
