summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/ARM/sat-arith.ll
Commit message (Collapse)AuthorAgeFilesLines
* [ARM] ACLE Chapter 9 intrinsicsSam Parker2017-05-041-63/+0
| | | | | | | | | | | | Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructions for ↵Weiming Zhao2015-12-201-11/+14
| | | | | | | | | | | | | | | | | Thumb2 Summary: r250697 fixed the mapping for ARM mode. We have to do the same for Thumb2 otherwise the same llvm.arm.ssat() will generate different saturating amount for ARM and Thumb. r250697: http://reviews.llvm.org/rL250697 Reviewers: rmaprath Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D15653 llvm-svn: 256115
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructionsAsiri Rathnayake2015-10-191-0/+60
The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
OpenPOWER on IntegriCloud