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authorSam Parker <sam.parker@arm.com>2017-05-04 07:31:28 +0000
committerSam Parker <sam.parker@arm.com>2017-05-04 07:31:28 +0000
commitdf337704f0ba643eaaa09883625837622b858c32 (patch)
tree9314cb3be30480464c2dcf871a6d003a6d78b746 /llvm/test/CodeGen/ARM/sat-arith.ll
parentbe6da4bbdb34377633d3725eeb3184be8f05c679 (diff)
downloadbcm5719-llvm-df337704f0ba643eaaa09883625837622b858c32.tar.gz
bcm5719-llvm-df337704f0ba643eaaa09883625837622b858c32.zip
[ARM] ACLE Chapter 9 intrinsics
Added the integer data processing intrinsics from ACLE v2.1 Chapter 9 but I have missed out the saturation_occurred intrinsics for now. For the instructions that read and write the GE bits, a chain is included and the only instruction that reads these flags (sel) is only selectable via the implemented intrinsic. Differential Revision: https://reviews.llvm.org/D32281 llvm-svn: 302126
Diffstat (limited to 'llvm/test/CodeGen/ARM/sat-arith.ll')
-rw-r--r--llvm/test/CodeGen/ARM/sat-arith.ll63
1 files changed, 0 insertions, 63 deletions
diff --git a/llvm/test/CodeGen/ARM/sat-arith.ll b/llvm/test/CodeGen/ARM/sat-arith.ll
deleted file mode 100644
index 4844ed1bd21..00000000000
--- a/llvm/test/CodeGen/ARM/sat-arith.ll
+++ /dev/null
@@ -1,63 +0,0 @@
-; RUN: llc -O1 -mtriple=armv6-none-none-eabi %s -o - | FileCheck %s -check-prefix=ARM -check-prefix=CHECK
-; RUN: llc -O1 -mtriple=thumbv7-none-none-eabi %s -o - | FileCheck %s -check-prefix=THUMB -check-prefix=CHECK
-
-; CHECK-LABEL: qadd
-define i32 @qadd() nounwind {
-; CHECK-DAG: mov{{s?}} [[R0:.*]], #8
-; CHECK-DAG: mov{{s?}} [[R1:.*]], #128
-; CHECK-ARM: qadd [[R0]], [[R1]], [[R0]]
-; CHECK-THRUMB: qadd [[R0]], [[R0]], [[R1]]
- %tmp = call i32 @llvm.arm.qadd(i32 128, i32 8)
- ret i32 %tmp
-}
-
-; CHECK-LABEL: qsub
-define i32 @qsub() nounwind {
-; CHECK-DAG: mov{{s?}} [[R0:.*]], #8
-; CHECK-DAG: mov{{s?}} [[R1:.*]], #128
-; CHECK-ARM: qsub [[R0]], [[R1]], [[R0]]
-; CHECK-THRUMB: qadd [[R0]], [[R1]], [[R0]]
- %tmp = call i32 @llvm.arm.qsub(i32 128, i32 8)
- ret i32 %tmp
-}
-
-; upper-bound of the immediate argument
-; CHECK-LABEL: ssat1
-define i32 @ssat1() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: ssat [[R1:.*]], #32, [[R0]]
- %tmp = call i32 @llvm.arm.ssat(i32 128, i32 32)
- ret i32 %tmp
-}
-
-; lower-bound of the immediate argument
-; CHECK-LABEL: ssat2
-define i32 @ssat2() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: ssat [[R1:.*]], #1, [[R0]]
- %tmp = call i32 @llvm.arm.ssat(i32 128, i32 1)
- ret i32 %tmp
-}
-
-; upper-bound of the immediate argument
-; CHECK-LABEL: usat1
-define i32 @usat1() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: usat [[R1:.*]], #31, [[R0]]
- %tmp = call i32 @llvm.arm.usat(i32 128, i32 31)
- ret i32 %tmp
-}
-
-; lower-bound of the immediate argument
-; CHECK-LABEL: usat2
-define i32 @usat2() nounwind {
-; CHECK: mov{{s?}} [[R0:.*]], #128
-; CHECK: usat [[R1:.*]], #0, [[R0]]
- %tmp = call i32 @llvm.arm.usat(i32 128, i32 0)
- ret i32 %tmp
-}
-
-declare i32 @llvm.arm.qadd(i32, i32) nounwind
-declare i32 @llvm.arm.qsub(i32, i32) nounwind
-declare i32 @llvm.arm.ssat(i32, i32) nounwind readnone
-declare i32 @llvm.arm.usat(i32, i32) nounwind readnone
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