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* Change some ARM subtarget features to be single bit yes/no in order to sink ↵Evan Cheng2011-07-071-2/+2
| | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590
* Since ARM's prefetch implementation predicted the presence of a instructionBruno Cardoso Lopes2011-06-141-0/+11
| | | | | | | cache prefetch and now that the info from "prefetch" to "ARMPreload" is present, only add a testcase for PLI. llvm-svn: 132978
* Add one more argument to the prefetch intrinsic to indicate whether it's a dataBruno Cardoso Lopes2011-06-141-6/+6
| | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976
* Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637.Bob Wilson2011-04-191-8/+13
| | | | llvm-svn: 129774
* Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵Evan Cheng2010-11-041-16/+13
| | | | | | immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237
* Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵Evan Cheng2010-11-031-2/+2
| | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160
* Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536.Evan Cheng2010-11-031-0/+64
llvm-svn: 118152
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