| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Change some ARM subtarget features to be single bit yes/no in order to sink ↵ | Evan Cheng | 2011-07-07 | 1 | -2/+2 |
| | | | | | | | them down to MC layer. Also fix tests. llvm-svn: 134590 | ||||
| * | Since ARM's prefetch implementation predicted the presence of a instruction | Bruno Cardoso Lopes | 2011-06-14 | 1 | -0/+11 |
| | | | | | | | | cache prefetch and now that the info from "prefetch" to "ARMPreload" is present, only add a testcase for PLI. llvm-svn: 132978 | ||||
| * | Add one more argument to the prefetch intrinsic to indicate whether it's a data | Bruno Cardoso Lopes | 2011-06-14 | 1 | -6/+6 |
| | | | | | | | | or instruction cache access. Update the targets to match it and also teach autoupgrade. llvm-svn: 132976 | ||||
| * | Add -mcpu=cortex-a9-mp. It's cortex-a9 with MP extension. rdar://8648637. | Bob Wilson | 2011-04-19 | 1 | -8/+13 |
| | | | | | llvm-svn: 129774 | ||||
| * | Fix @llvm.prefetch isel. Selecting between pld / pldw using the first ↵ | Evan Cheng | 2010-11-04 | 1 | -16/+13 |
| | | | | | | | immediate rw. There is currently no intrinsic that matches to pli. llvm-svn: 118237 | ||||
| * | Fix preload instruction isel. Only v7 supports pli, and only v7 with mp ↵ | Evan Cheng | 2010-11-03 | 1 | -2/+2 |
| | | | | | | | extension supports pldw. Add subtarget attribute to denote mp extension support and legalize illegal ones to nothing. llvm-svn: 118160 | ||||
| * | Add support to match @llvm.prefetch to pld / pldw / pli. rdar://8601536. | Evan Cheng | 2010-11-03 | 1 | -0/+64 |
| llvm-svn: 118152 | |||||

