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* [ARM] Avoid using ARM instructions in Thumb modeSam Parker2017-01-311-1/+0
| | | | | | | | | | | | | | The Requires class overrides the target requirements of an instruction, rather than adding to them, so all ARM instructions need to include the IsARM predicate when they have overwitten requirements. This caused the swp and swpb instructions to be allowed in thumb mode assembly, and the ARM encoding of CDP to be selected in codegen (which is different for conditional instructions). Differential Revision: https://reviews.llvm.org/D29283 llvm-svn: 293634
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-171-0/+8
| | | | | | | | | | | | | | | | | | | Reapplying patch as it was reverted when it was first committed because of an assertion failure when the mrrc2 intrinsic was called in ARM mode. The failure was happening because the instruction was being built in ARMISelDAGToDAG.cpp and the tablegen description for mrrc2 instruction doesn't allow you to use a predicate. The ARM architecture manuals do say that mrrc2 in ARM mode can be predicated with AL in assembly but this has no effect on the encoding of the instruction as the top 4 bits will always be 1111 not 1110 which is the encoding for the condition AL. Differential Revision: http://reviews.llvm.org/D21408 llvm-svn: 272982
* Reverting r272778 because there's an assertionRanjeet Singh2016-06-151-8/+0
| | | | | | failure when running the test CodeGen/ARM/intrinsics-coprocessor.ll llvm-svn: 272791
* [ARM] Add support for mrrc/mrrc2 intrinsics.Ranjeet Singh2016-06-151-0/+8
| | | | | | Differential Revision: http://reviews.llvm.org/D21178 llvm-svn: 272778
* [ARM] Reverting r272544 because clang patch needsRanjeet Singh2016-06-131-8/+0
| | | | | | | to go in as soon as llvm patch has gone in because tests will start breaking in Clang. llvm-svn: 272546
* [ARM] Add mrrc/mrrc2 co-processor intrinsicsRanjeet Singh2016-06-131-0/+8
| | | | | | | | | | | | | MRRC/MRRC2 instruction writes to two registers. The intrinsic definition returns a single uint64_t to represent the write, this is a compact way of representing a write to two 32 bit registers, the alternative might have been two return a struct of 2 uint32_t's but this isn't as nice. Differential Revision: llvm-svn: 272544
* [ARM] Add backend support for load/store intrinsics.Ranjeet Singh2016-05-311-7/+39
| | | | | | | | | | Added support to map intrinsics __builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l} to their ARM instructions. Differential Revision: http://reviews.llvm.org/D20564 llvm-svn: 271271
* [ARM] Add cdp intrinsic tests.Ranjeet Singh2016-05-191-0/+39
- Renamed intrinsics.ll to intrinsics-coprocessor.ll as all the tests were testing coprocessor instructions, also made the test checks match the full instruction. Differential Revision: http://reviews.llvm.org/D20393 llvm-svn: 270057
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