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| author | Ranjeet Singh <Ranjeet.Singh@arm.com> | 2016-05-31 12:39:30 +0000 |
|---|---|---|
| committer | Ranjeet Singh <Ranjeet.Singh@arm.com> | 2016-05-31 12:39:30 +0000 |
| commit | 16c24f4d6e2a1ca64d2482289e3985d0b0d7d9e3 (patch) | |
| tree | bf1d31c991e968054140170781ef2c9859a04880 /llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll | |
| parent | 03016b85b6e21992f6d50c91c9be5cb8a5341f5c (diff) | |
| download | bcm5719-llvm-16c24f4d6e2a1ca64d2482289e3985d0b0d7d9e3.tar.gz bcm5719-llvm-16c24f4d6e2a1ca64d2482289e3985d0b0d7d9e3.zip | |
[ARM] Add backend support for load/store intrinsics.
Added support to map intrinsics
__builtin_arm_{ldc,ldcl,ldc2,ldc2l,stc,stcl,stc2,stc2l}
to their ARM instructions.
Differential Revision: http://reviews.llvm.org/D20564
llvm-svn: 271271
Diffstat (limited to 'llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll')
| -rw-r--r-- | llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll | 46 |
1 files changed, 39 insertions, 7 deletions
diff --git a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll index 35f916c4a26..ccaf5c29fad 100644 --- a/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll +++ b/llvm/test/CodeGen/ARM/intrinsics-coprocessor.ll @@ -1,27 +1,59 @@ ; RUN: llc < %s -mtriple=armv7-eabi -mcpu=cortex-a8 | FileCheck %s ; RUN: llc < %s -march=thumb -mtriple=thumbv7-eabi -mcpu=cortex-a8 | FileCheck %s -define void @coproc() nounwind { +define void @coproc(i8* %i) nounwind { entry: - ; CHECK: mrc p7, #1, r0, c1, c1, #4 + ; CHECK: mrc p7, #1, r{{[0-9]+}}, c1, c1, #4 %0 = tail call i32 @llvm.arm.mrc(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind - ; CHECK: mcr p7, #1, r0, c1, c1, #4 + ; CHECK: mcr p7, #1, r{{[0-9]+}}, c1, c1, #4 tail call void @llvm.arm.mcr(i32 7, i32 1, i32 %0, i32 1, i32 1, i32 4) nounwind - ; CHECK: mrc2 p7, #1, r1, c1, c1, #4 + ; CHECK: mrc2 p7, #1, r{{[0-9]+}}, c1, c1, #4 %1 = tail call i32 @llvm.arm.mrc2(i32 7, i32 1, i32 1, i32 1, i32 4) nounwind - ; CHECK: mcr2 p7, #1, r1, c1, c1, #4 + ; CHECK: mcr2 p7, #1, r{{[0-9]+}}, c1, c1, #4 tail call void @llvm.arm.mcr2(i32 7, i32 1, i32 %1, i32 1, i32 1, i32 4) nounwind - ; CHECK: mcrr p7, #1, r0, r1, c1 + ; CHECK: mcrr p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1 tail call void @llvm.arm.mcrr(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind - ; CHECK: mcrr2 p7, #1, r0, r1, c1 + ; CHECK: mcrr2 p7, #1, r{{[0-9]+}}, r{{[0-9]+}}, c1 tail call void @llvm.arm.mcrr2(i32 7, i32 1, i32 %0, i32 %1, i32 1) nounwind ; CHECK: cdp p7, #3, c1, c1, c1, #5 tail call void @llvm.arm.cdp(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind ; CHECK: cdp2 p7, #3, c1, c1, c1, #5 tail call void @llvm.arm.cdp2(i32 7, i32 3, i32 1, i32 1, i32 1, i32 5) nounwind + ; CHECK: ldc p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldc(i32 7, i32 3, i8* %i) nounwind + ; CHECK: ldcl p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldcl(i32 7, i32 3, i8* %i) nounwind + ; CHECK: ldc2 p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldc2(i32 7, i32 3, i8* %i) nounwind + ; CHECK: ldc2l p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.ldc2l(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stc p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stc(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stcl p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stcl(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stc2 p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stc2(i32 7, i32 3, i8* %i) nounwind + ; CHECK: stc2l p7, c3, [r{{[0-9]+}}] + tail call void @llvm.arm.stc2l(i32 7, i32 3, i8* %i) nounwind ret void } +declare void @llvm.arm.ldc(i32, i32, i8*) nounwind + +declare void @llvm.arm.ldcl(i32, i32, i8*) nounwind + +declare void @llvm.arm.ldc2(i32, i32, i8*) nounwind + +declare void @llvm.arm.ldc2l(i32, i32, i8*) nounwind + +declare void @llvm.arm.stc(i32, i32, i8*) nounwind + +declare void @llvm.arm.stcl(i32, i32, i8*) nounwind + +declare void @llvm.arm.stc2(i32, i32, i8*) nounwind + +declare void @llvm.arm.stc2l(i32, i32, i8*) nounwind + declare void @llvm.arm.cdp2(i32, i32, i32, i32, i32, i32) nounwind declare void @llvm.arm.cdp(i32, i32, i32, i32, i32, i32) nounwind |
