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* AMDGPU: Remove unnecessary IR from testMatt Arsenault2019-10-141-63/+9
* [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperatorCameron McInally2019-10-142-53/+53
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-1442-315/+354
* [AMDGPU] Use GCN prefix in dpp_combine.mir. NFC.Stanislav Mekhanoshin2019-10-111-82/+82
* [AMDGPU] link dpp pseudos and real instructions on gfx10Stanislav Mekhanoshin2019-10-112-271/+5008
* [GISel] Allow getConstantVRegVal() to return G_FCONSTANT values.Marcello Maggioni2019-10-101-22/+14
* [AMDGPU] Handle undef old operand in DPP combineStanislav Mekhanoshin2019-10-101-1/+12
* [AMDGPU] Fixed dpp_combine.mir with expensive checks. NFC.Stanislav Mekhanoshin2019-10-101-5/+7
* Revert "[IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperator"Dmitri Gribenko2019-10-102-53/+53
* AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault2019-10-1044-331/+331
* AMDGPU: Don't fold copies to physregsMatt Arsenault2019-10-091-1/+1
* AMDGPU/GlobalISel: Fix crash on wide constant load with VGPR pointerMatt Arsenault2019-10-091-0/+46
* GlobalISel: Implement fewerElementsVector for G_BUILD_VECTORMatt Arsenault2019-10-0928-672/+1284
* [AMDGPU] Fixed dpp combine of VOP1Stanislav Mekhanoshin2019-10-091-0/+23
* [IRBuilder] Update IRBuilder::CreateFNeg(...) to return a UnaryOperatorCameron McInally2019-10-092-53/+53
* AMDGPU: Fix i16 arithmetic pattern redundancyMatt Arsenault2019-10-0810-329/+367
* AMDGPU: Add offsets to MMO when lowering buffer intrinsicsTom Stellard2019-10-081-0/+414
* (Re)generate various tests. NFCAmaury Sechet2019-10-082-128/+997
* AMDGPU: Propagate undef flag during pre-RA exec mask optimizationsNicolai Haehnle2019-10-081-1/+24
* MachineSSAUpdater: insert IMPLICIT_DEF at top of basic blockNicolai Haehnle2019-10-081-0/+28
* AMDGPU/GlobalISel: Clamp G_SITOFP/G_UITOFP sourcesMatt Arsenault2019-10-072-146/+575
* AMDGPU/GlobalISel: Handle more G_INSERT casesMatt Arsenault2019-10-071-20/+130
* GlobalISel: Partially implement lower for G_INSERTMatt Arsenault2019-10-071-6/+148
* AMDGPU/GlobalISel: Fix selection of 16-bit shiftsMatt Arsenault2019-10-073-294/+810
* AMDGPU/GlobalISel: Select VALU G_AMDGPU_FFBH_U32Matt Arsenault2019-10-071-7/+7
* AMDGPU/GlobalISel: Use S_MOV_B64 for inline constantsMatt Arsenault2019-10-072-11/+12
* AMDGPU/GlobalISel: Widen 16-bit G_MERGE_VALUEs sourcesMatt Arsenault2019-10-077-5451/+11837
* AMDGPU/GlobalISel: Select more G_INSERT casesMatt Arsenault2019-10-071-22/+425
* GlobalISel: Add target pre-isel instructionsMatt Arsenault2019-10-072-0/+100
* [AMDGPU] Fix test checksJay Foad2019-10-071-2/+4
* AMDGPU/GlobalISel: RegBankSelect DS GWS intrinsicsMatt Arsenault2019-10-062-0/+116
* AMDGPU/GlobalISel: Lower G_ATOMIC_CMPXCHG_WITH_SUCCESSMatt Arsenault2019-10-061-0/+107
* GlobalISel: Partially implement lower for G_EXTRACTMatt Arsenault2019-10-064-24/+213
* AMDGPU/GlobalISel: Fix RegBankSelect for sendmsg intrinsicsMatt Arsenault2019-10-063-25/+11
* AMDGPU/GlobalISel: Fix using wrong addrspace for apertureMatt Arsenault2019-10-041-8/+8
* AMDGPU/GlobalISel: Select G_PTRTOINTMatt Arsenault2019-10-041-0/+101
* AMDGPU/GlobalISel: Support wave32 waterfall loopsMatt Arsenault2019-10-0412-389/+704
* AMDGPU/GlobalISel: Handle RegBankSelect of G_INSERT_VECTOR_ELTMatt Arsenault2019-10-031-12/+383
* AMDGPU/GlobalISel: Split 64-bit vector extracts during RegBankSelectMatt Arsenault2019-10-031-6/+114
* AMDGPU/GlobalISel: Allow VGPR to index SGPR registerMatt Arsenault2019-10-031-3/+2
* AMDGPU/GlobalISel: Add some more tests for G_INSERT legalizationMatt Arsenault2019-10-031-0/+168
* AMDGPU/GlobalISel: Fix mutationIsSane assert v8s8 andMatt Arsenault2019-10-031-0/+166
* AMDGPU/GlobalISel: Expand G_BITCAST legalityMatt Arsenault2019-10-031-0/+102
* [AMDGPU] Fix illegal agpr use by VALUStanislav Mekhanoshin2019-10-022-3/+21
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-0256-454/+525
* AMDGPU/GlobalISel: Assume VGPR for G_FRAME_INDEXMatt Arsenault2019-10-021-1/+1
* AMDGPU/GlobalISel: Private loads always use VGPRsMatt Arsenault2019-10-021-0/+17
* AMDGPU/GlobalISel: Legalize 1024-bit G_BUILD_VECTORMatt Arsenault2019-10-022-40/+155
* AMDGPU/GlobalISel: Fix RegBankSelect for 1024-bit valuesMatt Arsenault2019-10-021-0/+28
* [AMDGPU] separate accounting for agprsStanislav Mekhanoshin2019-10-021-10/+129
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