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* AMDGPU/GlobalISel: Add InstrMapping for G_EXTRACTMatt Arsenault2018-03-051-0/+31
| | | | llvm-svn: 326715
* AMDGPU/GlobalISel: Make some G_EXTRACTs legalMatt Arsenault2018-03-051-0/+105
| | | | | | | As far as I can tell legalization of weird sizes for the output type isn't implemented. llvm-svn: 326714
* Pass Divergence Analysis data to Selection DAG to drive divergenceAlexander Timofeev2018-03-052-16/+59
| | | | | | | | dependent instruction selection. Differential revision: https://reviews.llvm.org/D35267 llvm-svn: 326703
* AMDGPU/GlobalISel: InstrMapping for G_ZEXTMatt Arsenault2018-03-021-0/+31
| | | | llvm-svn: 326589
* AMDGPU/GlobalISel: InstrMapping for G_TRUNCMatt Arsenault2018-03-021-0/+31
| | | | llvm-svn: 326588
* AMDGPU/GlobalISel: Define InstrMappings for G_FCMPMatt Arsenault2018-03-021-0/+69
| | | | | | Patch by Tom Stellard llvm-svn: 326587
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.minnumMatt Arsenault2018-03-021-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326586
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.maxnumMatt Arsenault2018-03-021-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326567
* AMDGPU/GCN: Promote i16 ctpopJan Vesely2018-03-021-0/+334
| | | | | | | | | i16 capable ASICs do not support i16 operands for this instruction. Add tablegen pattern to merge chained i16 additions. Differential Revision: https://reviews.llvm.org/D43985 llvm-svn: 326535
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOSIMatt Arsenault2018-03-021-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326534
* AMDGPU/GlobalISel: Define instruction mapping for G_FPTOUIMatt Arsenault2018-03-021-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326533
* AMDGPU/GlobalISel: Define instruction mapping for G_FMULMatt Arsenault2018-03-021-0/+69
| | | | llvm-svn: 326532
* AMDGPU/GlobalISel: Define instruction mapping for G_FADDMatt Arsenault2018-03-021-0/+69
| | | | | | Patch by Tom Stellard llvm-svn: 326526
* AMDGPU/GlobalISel: Define instruction mapping for G_SHLMatt Arsenault2018-03-021-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326525
* AMDGPU/GlobalISel: Define instruction mapping for G_XORMatt Arsenault2018-03-021-0/+68
| | | | llvm-svn: 326524
* AMDGPU/GlobalISel: Define instruction mapping for G_ANDMatt Arsenault2018-03-021-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326523
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.cvt.pkrtzMatt Arsenault2018-03-011-0/+66
| | | | | | Patch by Tom Stellard llvm-svn: 326490
* AMDGPU/GlobalISel: Define instruction mapping for G_ORMatt Arsenault2018-03-011-0/+68
| | | | | | Patch by Tom Stellard llvm-svn: 326489
* AMDGPU/GlobalISel: Define instruction mapping for G_BITCASTMatt Arsenault2018-03-011-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326482
* AMDGPU/GlobalISel: Mark i32->i64 zext as legalMatt Arsenault2018-03-011-0/+14
| | | | llvm-svn: 326481
* AMDGPU/GlobalISel: InstrMapping for llvm.amdgcn.exp.comprMatt Arsenault2018-03-011-0/+67
| | | | | | Patch by Tom Stellard llvm-svn: 326479
* AMDGPU/GlobalISel: Define instruction mapping for @llvm.amdgcn.expMatt Arsenault2018-03-011-0/+77
| | | | | | Patch by Tom Stellard llvm-svn: 326477
* AMDGPU/GlobalISel: Define InstrMappings for G_ICMPMatt Arsenault2018-03-011-0/+67
| | | | | | Patch by Tom Stellard llvm-svn: 326472
* AMDGPU/GlobalISel: Make i32 mul legalMatt Arsenault2018-03-011-0/+18
| | | | llvm-svn: 326471
* AMDGPU/GlobalISel: Define instruction mapping for G_IMPLICIT_DEFMatt Arsenault2018-03-011-6/+27
| | | | | | Patch by Tom Stellard llvm-svn: 326470
* AMDGPU/GlobalISel: Define instruction mapping for G_FCONSTANTMatt Arsenault2018-03-011-0/+31
| | | | | | Patch by Tom Stellard llvm-svn: 326468
* AMDGPU/GlobalISel: Make i32 xor legalMatt Arsenault2018-03-011-0/+18
| | | | llvm-svn: 326466
* AMDGPU/GlobalISel: Mark 32/64-bit G_FCMP as legalMatt Arsenault2018-03-011-0/+35
| | | | | | Patch by Tom Stellard llvm-svn: 326465
* AMDGPU/GlobalISel: Mark 32-bit G_FPTOSI as legalMatt Arsenault2018-03-011-0/+14
| | | | | | Patch by Tom Stellard llvm-svn: 326464
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-285-15/+95
| | | | | | | | | | | | | | | | | Summary: For use by LLPC SPV_AMD_shader_ballot extension. The v_writelane instruction was already implemented for use by SGPR spilling, but I had to add an extra dummy operand tied to the destination, to represent that all lanes except the selected one keep the old value of the destination register. .ll test changes were due to schedule changes caused by that new operand. Differential Revision: https://reviews.llvm.org/D42838 llvm-svn: 326353
* Re-enable "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Geoff Berry2018-02-274-17/+17
| | | | | | | | Re-enable commit r323991 now that r325931 has been committed to make MachineOperand::isRenamable() check more conservative w.r.t. code changes and opt-in on a per-target basis. llvm-svn: 326208
* AMDGPU/GlobalISel: Make f64 constants legalMatt Arsenault2018-02-261-10/+51
| | | | llvm-svn: 326101
* [AMDGPU] Scratch setup fix on AMDPAL gfx9+ merge shaderTim Renouf2018-02-261-0/+34
| | | | | | | | | | | | | | | | Summary: With OS type AMDPAL, the scratch descriptor is hardwired to be loaded from offset 0 of the global information table, whose low pointer is passed in s0. For a merge shader on gfx9+, it needs to be s8 instead, as the hardware reserves s0-s7. Reviewers: kzhuravl Subscribers: arsenm, nhaehnle, dstuttard, llvm-commits, t-tye, yaxunl, wdng, kzhuravl Differential Revision: https://reviews.llvm.org/D42203 llvm-svn: 326088
* Revert "StructurizeCFG: Test for branch divergence correctly"Adam Nemet2018-02-241-2/+2
| | | | | | | | This reverts commit r325881. Breaks many bots llvm-svn: 326037
* [AMDGPU] Shrinking V_SUBBREV_U32Stanislav Mekhanoshin2018-02-242-6/+6
| | | | | | | | | | V_SUBBREV_U32 is a commute opcode for V_SUBB_U32. However, when we try to commute V_SUBB_U32 in order to shrink it we do not then process V_SUBBREV_U32 and it stay VOP3. This is fixed. Differential Revision: https://reviews.llvm.org/D43699 llvm-svn: 326011
* [AMDGPU] Fixed madak.ll test on VI, added GFX10. NFC.Stanislav Mekhanoshin2018-02-231-33/+45
| | | | llvm-svn: 325995
* [MachineOperand][Target] MachineOperand::isRenamable semantics changesGeoff Berry2018-02-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: Add a target option AllowRegisterRenaming that is used to opt in to post-register-allocation renaming of registers. This is set to 0 by default, which causes the hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq fields of all opcodes to be set to 1, causing MachineOperand::isRenamable to always return false. Set the AllowRegisterRenaming flag to 1 for all in-tree targets that have lit tests that were effected by enabling COPY forwarding in MachineCopyPropagation (AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISCV, Sparc, SystemZ and X86). Add some more comments describing the semantics of the MachineOperand::isRenamable function and how it is set and maintained. Change isRenamable to check the operand's opcode hasExtraSrcRegAllocReq/hasExtraDstRegAllocReq bit directly instead of relying on it being consistently reflected in the IsRenamable bit setting. Clear the IsRenamable bit when changing an operand's register value. Remove target code that was clearing the IsRenamable bit when changing registers/opcodes now that this is done conservatively by default. Change setting of hasExtraSrcRegAllocReq in AMDGPU target to be done in one place covering all opcodes that have constant pipe read limit restrictions. Reviewers: qcolombet, MatzeB Subscribers: aemerson, arsenm, jyknight, mcrosier, sdardis, nhaehnle, javed.absar, tpr, arichardson, kristof.beyls, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, jordy.potman.lists, apazos, sabuasal, niosHD, escha, nemanjai, llvm-commits Differential Revision: https://reviews.llvm.org/D43042 llvm-svn: 325931
* [DAGCOmbine] Ensure that (brcond (setcc ...)) is handled in a canonical manner.Amaury Sechet2018-02-232-5/+3
| | | | | | | | | | | | | | | Summary: There are transformation that change setcc into other constructs, and transform that try to reconstruct a setcc from the brcond condition. Depending on what order these transform are done, the end result differs. Most of the time, it is preferable to get a setcc as a brcond argument (and this is why brcond try to recreate the setcc in the first place) so we ensure this is done every time by also doing it at the setcc level when the only user is a brcond. Reviewers: spatel, hfinkel, niravd, craig.topper Subscribers: nhaehnle, llvm-commits Differential Revision: https://reviews.llvm.org/D41235 llvm-svn: 325892
* AMDGPU: Track physreg uses in SILoadStoreOptimizerNicolai Haehnle2018-02-233-10/+158
| | | | | | | | | | | | | | | | Summary: This handles def-after-use of physregs, and allows us to merge loads and stores even across some physreg defs (typically M0 defs). Change-Id: I076484b2bda27c2cf46013c845a0380c5b89b67b Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D42647 llvm-svn: 325882
* StructurizeCFG: Test for branch divergence correctlyNicolai Haehnle2018-02-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | Summary: This fixes cases like the new test @nonuniform. In that test, %cc itself is a uniform value; however, when reading it after the end of the loop in basic block %if, its value is effectively non-uniform. This problem was encountered in https://bugs.freedesktop.org/show_bug.cgi?id=103743; however, this change in itself is not sufficient to fix that bug, as there is another issue in the AMDGPU backend. Change-Id: I32bbffece4a32f686fab54964dae1a5dd72949d4 Reviewers: arsenm, rampitec, jlebar Subscribers: wdng, tpr, llvm-commits Differential Revision: https://reviews.llvm.org/D40546 llvm-svn: 325881
* AMDGPU: Do not combine loads/store across physreg defsNicolai Haehnle2018-02-213-15/+83
| | | | | | | | | | | | | | | | | | | Summary: Since this pass operates on machine SSA form, this should only really affect M0 in practice. Fixes various piglit variable-indexing/vs-varying-array-mat4-index-* Change-Id: Ib2a1dc3a8d7b08225a8da49a86f533faa0986aa8 Fixes: r317751 ("AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4") Reviewers: arsenm, mareko, rampitec Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D40343 llvm-svn: 325677
* Revert "[AMDGPU] Increased vector length for global/constant loads."Konstantin Zhuravlyov2018-02-203-71/+1
| | | | | | | | | | https://reviews.llvm.org/rL325518 It breaks following OpenCL conformance tests: - Basic - parameter_types - Basic - vload_private llvm-svn: 325643
* [AMDGPU] Removed redundant run lines for fmuladd.f16 test. NFC.Stanislav Mekhanoshin2018-02-201-4/+0
| | | | llvm-svn: 325615
* [AMDGPU] stop buffer_store being moved illegallyTim Renouf2018-02-201-0/+53
| | | | | | | | | | | | | | | Summary: The machine instruction scheduler was illegally moving a buffer store past a buffer load with the same descriptor and offset. Fixed by marking buffer ops as mayAlias and isAliased. This may be overly conservative, and we may need to revisit. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D43332 Change-Id: Iff3173d9e0653e830474546276ab9d30318b8ef7 llvm-svn: 325567
* [AMDGPU] Make note of existing waitcnt instrs; this is add-on work related ↵Mark Searles2018-02-191-11/+12
| | | | | | to suppression of redundant waitcnt instrs. It is necessary to make note of these existing waitcnt instrs so that we do not fall into an infinite loop when handling loops. Also, [NFC] some minor code clean-up. llvm-svn: 325524
* [AMDGPU] Increased vector length for global/constant loads.Mark Searles2018-02-193-1/+71
| | | | | | | | | | | | | | Summary: GCN ISA supports instructions that can read 16 consecutive dwords from memory through the scalar data cache; loadstoreVectorizer should take advantage of the wider vector length and pack 16/8 elements of dwords/quadwords. Author: FarhanaAleen Reviewed By: rampitec Subscribers: llvm-commits, AMDGPU Differential Revision: https://reviews.llvm.org/D43275 llvm-svn: 325518
* [AMDGPU] Return true in enableMultipleCopyHints().Jonas Paulsson2018-02-173-12/+12
| | | | | | | | | | Enable multiple COPY hints to eliminate more COPYs during register allocation. Note that this is something all targets should do, see https://reviews.llvm.org/D38128. Review: Stanislav Mekhanoshin, Tom Stellard. llvm-svn: 325425
* Revert "[MachineCopyPropagation] Extend pass to do COPY source forwarding"Quentin Colombet2018-02-174-16/+16
| | | | | | | | | | | | | | | | | This reverts commit r323991. This commit breaks target that don't model all the register constraints in TableGen. So far the workaround was to set the hasExtraXXXRegAllocReq, but it proves that it doesn't cover all the cases. For instance, when mutating an instruction (like in the lowering of COPYs) the isRenamable flag is not properly updated. The same problem will happen when attaching machine operand from one instruction to another. Geoff Berry is working on a fix in https://reviews.llvm.org/D43042. llvm-svn: 325421
* AMDGPU: Bring elf flags in sync with the specKonstantin Zhuravlyov2018-02-164-49/+124
| | | | | | | | | | | - Add MACH flags - Add XNACK flag - Add reserved flags - Minor cleanups in docs Differential Revision: https://reviews.llvm.org/D43356 llvm-svn: 325399
* AMDGPU: Bring processors and features in sync with the specKonstantin Zhuravlyov2018-02-166-23/+21
| | | | | | | | | | - Remove gfx800 - Make iceland gfx802 - Add xnack to gfx902 Differential Revision: https://reviews.llvm.org/D43355 llvm-svn: 325393
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