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* Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle2020-02-031-17/+25
* [AMDGPU] Invert the handling of skip insertion.cdevadas2020-01-151-25/+17
* [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer...vpykhtin2019-11-261-3/+2
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-141-3/+3
* [MBP] Move a latch block with conditional exit and multi predecessors to top ...Guozhi Wei2019-06-141-1/+1
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-3/+3
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-3/+3
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-3/+3
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-3/+3
* AMDGPU: Force skip over SMRD, VMEM and s_waitcnt instructionsRhys Perry2019-04-171-0/+3
* [LowerSwitch][AMDGPU] Do not handle impossible valuesRoman Tereshin2019-02-221-4/+4
* AMDGPU: Rewrite SILowerI1Copies to always stay on SALUNicolai Haehnle2018-10-311-9/+9
* AMDGPU: Remove PHI loop condition optimizationNicolai Haehnle2018-10-311-7/+3
* [AMDGPU] Preliminary patch for divergence driven instruction selection. Immed...Alexander Timofeev2018-09-111-0/+1
* [AMDGPU] Avoid using divergent value in mubuf addr64 descriptorTim Renouf2018-08-021-2/+1
* AMDGPU: Don't use struct type for argument layoutMatt Arsenault2018-06-291-1/+1
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-1/+1
* [AMDGPU] Fixed incorrect break from loopTim Renouf2018-05-251-1/+3
* [AMDGPU] Revert b0efc4fd6 (https://reviews.llvm.org/D40556)Alexander Timofeev2018-04-251-2/+2
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-1/+1
* [AMDGPU] SiFixSGPRCopies should not modify non-divergent PHIAlexander Timofeev2017-12-011-2/+2
* [AMDGPU] Eliminate no effect instructions before s_endpgmStanislav Mekhanoshin2017-08-161-6/+0
* [AMDGPU] Optimize SI_IF lowering for simple if regionsStanislav Mekhanoshin2017-07-261-9/+6
* [AMDGPU] Turn on the new waitcnt insertion pass. Adjust tests.Mark Searles2017-06-021-6/+2
* AMDGPU : Fix common dominator of two incoming blocks terminates with uniform ...Wei Ding2017-04-121-2/+2
* AMDGPU: Unify divergent function exits.Matt Arsenault2017-03-241-6/+77
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-4/+4
* [AMDGPU] Remove getBidirectionalReasonRankStanislav Mekhanoshin2017-03-111-1/+1
* AMDGPU/SI: Avoid moving PHIs to VALU when phi values are defined in scalar br...Tom Stellard2016-11-291-3/+2
* [AMDGPU] Fix multiple vreg definitions in si-lower-control-flowStanislav Mekhanoshin2016-11-221-7/+7
* AMDGPU: Use unsigned compare for eq/neMatt Arsenault2016-09-301-5/+5
* AMDGPU: Split SILowerControlFlow into two piecesMatt Arsenault2016-08-221-9/+32
* AMDGPU: Change insertion point of si_mask_branchMatt Arsenault2016-08-101-5/+5
* AMDGPU: Handle cbranch vccz/vccnzMatt Arsenault2016-05-211-2/+1
* AMDGPU: Implement AnalyzeBranchMatt Arsenault2016-05-211-14/+13
* RegisterPressure: Fix default lanemask for missing regunit intervalsMatthias Braun2016-04-291-1/+1
* CodeGen: Correct specification of PHI nodesMatthias Braun2016-03-281-2/+2
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-6/+9
* AMDGPU: Remove some old intrinsic uses from testsMatt Arsenault2016-02-111-5/+5
* AMDGPU: Hack for VS_32 register pressureMatt Arsenault2015-11-061-2/+2
* AMDGPU: Improve accuracy of instruction rates for VOPCMatt Arsenault2015-09-251-6/+6
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+188
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