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path: root/llvm/test/CodeGen/AMDGPU/smrd.ll
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* [AMDGPU] gfx1010 core wave32 changesStanislav Mekhanoshin2019-06-201-0/+1
* AMDGPU/GFX10: Support DLC bit in llvm.amdgcn.s.buffer.load intrinsicNicolai Haehnle2019-06-161-42/+43
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-0/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-1/+0
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-0/+1
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-1/+0
* AMDGPU: Convert tests away from llvm.SI.load.constMatt Arsenault2019-01-171-34/+34
* AMDGPU: Allow f32 types for llvm.amdgcn.s.buffer.loadMatt Arsenault2018-12-071-1/+45
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-11-301-18/+27
* [AMDGPU] combine extractelement into several selectsStanislav Mekhanoshin2018-11-131-5/+7
* Add test case for the regression caused by r344696Nicolai Haehnle2018-11-081-0/+24
* Revert "AMDGPU: Divergence-driven selection of scalar buffer load intrinsics"Nicolai Haehnle2018-11-071-30/+20
* StructurizeCFG: Simplify inserted PHI nodesNicolai Haehnle2018-10-171-3/+4
* AMDGPU: Divergence-driven selection of scalar buffer load intrinsicsNicolai Haehnle2018-10-171-6/+61
* StructurizeCFG,AMDGPU: Test case of a redundant phi and codegen consequencesNicolai Haehnle2018-10-151-0/+34
* AMDGPU: Test showing a scalar buffer load deficiencyNicolai Haehnle2018-10-151-0/+23
* [AMDGPU] Add support for multi-dword s.buffer.load intrinsicTim Renouf2018-08-251-9/+187
* [AMDGPU] Enable LICM in the BE pipelineStanislav Mekhanoshin2018-06-291-0/+1
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-2/+2
* AMDGPU: Track physreg uses in SILoadStoreOptimizerNicolai Haehnle2018-02-231-10/+19
* AMDGPU: Do not combine loads/store across physreg defsNicolai Haehnle2018-02-211-0/+45
* [AMDGPU] Change constant addr space to 4Yaxun Liu2018-02-131-36/+36
* AMDGPU: Remove the s_buffer workaround for GFX9 chipsMarek Olsak2018-02-071-8/+2
* AMDGPU: Fix S_BUFFER_LOAD_DWORD_SGPR moveToVALUMarek Olsak2018-02-061-0/+34
* AMDGPU: Fold inline offset for loads properly in moveToVALU on GFX9Marek Olsak2018-01-311-15/+3
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-4/+4
* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-4/+16
* AMDGPU: Use stricter regexes for add instructionsMatt Arsenault2017-11-291-1/+1
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer v_{add/addc/sub/subrev/su...Dmitry Preobrazhensky2017-11-201-1/+1
* AMDGPU: Merge BUFFER_LOAD_DWORD_OFFEN into x2, x4Marek Olsak2017-11-091-0/+23
* AMDGPU: Merge S_BUFFER_LOAD_DWORD_IMM into x2, x4Marek Olsak2017-11-091-15/+41
* AMDGPU: Fold immediate offset into BUFFER_LOAD_DWORD lowered from SMEMMarek Olsak2017-11-091-0/+21
* AMDGPU: Select s_buffer_load_dword with a non-constant SGPR offsetMarek Olsak2017-10-311-0/+16
* AMDGPU: Handle s_buffer_load_dword hazard on SIMarek Olsak2017-10-261-0/+17
* AMDGPU: Remove SITypeRewriterMatt Arsenault2017-06-281-24/+24
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-6/+6
* AMDGPU: Remove some uses of llvm.SI.export in testsMatt Arsenault2017-02-221-57/+57
* Enable FeatureFlatForGlobal on Volcanic IslandsMatt Arsenault2017-01-241-1/+1
* AMDGPU: Add a shader calling conventionNicolai Haehnle2016-04-061-8/+7
* AMDGPU/SI: Add support for 32-bit immediate SMRD offsets on CITom Stellard2015-08-061-12/+17
* AMDGPU/SI: Use ComplexPatterns for SMRD addressing modesTom Stellard2015-08-061-0/+56
* AMDGPU: don't match vgpr loads for constant loadsMarek Olsak2015-07-271-7/+1
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+111
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