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* AMDGPU: Use gfx9 carry-less add/sub instructionsMatt Arsenault2017-11-301-9/+22
| | | | llvm-svn: 319491
* AMDGPU: Enable IPRAMatt Arsenault2017-11-281-3/+3
| | | | llvm-svn: 319256
* [AMDGPU] Fix SITargetLowering::LowerCall for pointer info of byval argumentYaxun Liu2017-11-221-26/+27
| | | | | | | | | | | SITargetLowering::LowerCall uses dummy pointer info for byval argument, which causes flat load instead of buffer load. This patch fixes that. Differential Revision: https://reviews.llvm.org/D40040 llvm-svn: 318844
* [AMDGPU][MC][GFX8][GFX9] Corrected names of integer ↵Dmitry Preobrazhensky2017-11-201-6/+6
| | | | | | | | | | | | v_{add/addc/sub/subrev/subb/subbrev} See bug 34765: https://bugs.llvm.org//show_bug.cgi?id=34765 Reviewers: tamazov, SamWot, arsenm, vpykhtin Differential Revision: https://reviews.llvm.org/D40088 llvm-svn: 318675
* AMDGPU: Make frame register caller preservedMatt Arsenault2017-09-141-1/+1
| | | | | | | | | | | | | Using SplitCSR for the frame register was very broken. Often the copies in the prolog and epilog were optimized out, in addition to them being inserted after the true prolog where the FP was clobbered. I have a hacky solution which works that continues to use split CSR, but for now this is simpler and will get to working programs. llvm-svn: 313274
* AMDGPU: Don't spill SP reg like a normal CSRMatt Arsenault2017-09-131-0/+2
| | | | llvm-svn: 313217
* AMDGPU: Fix not accounting for tail call resource usageMatt Arsenault2017-09-051-0/+31
| | | | | | | | If the only call in a function is a tail call, the function isn't considered to have a call since it's a type of return. llvm-svn: 312561
* AMDGPU: Start adding tail call supportMatt Arsenault2017-08-111-0/+225
Handle the sibling call cases. llvm-svn: 310753
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