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path: root/llvm/test/CodeGen/AMDGPU/si-instr-info-correct-implicit-operands.ll
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* Rename ExpandISelPseudo->FinalizeISel, delay register reservationMatt Arsenault2019-06-191-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-1/+1
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-241-1/+1
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-1/+1
* AMDGPU/SI: Avoid creating unnecessary copies in the SIFixSGPRCopies passTom Stellard2016-11-161-1/+1
* [MIR] Print on the given output instead of stderr.Quentin Colombet2016-07-131-1/+1
* AMDGPU: Run SIFoldOperands after PeepholeOptimizerMatt Arsenault2016-04-141-1/+1
* AMDGPU: Add volatile to test loads and storesMatt Arsenault2016-04-121-2/+2
* AMDGPU: Don't reserve SCRATCH_PTR input registerMatt Arsenault2015-11-301-1/+1
* AMDGPU: Fix verifier error in SIFoldOperandsMatt Arsenault2015-10-211-1/+1
* AMDGPU/SI: Add implicit register operands in the correct order.Alex Lorenz2015-07-311-0/+16
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