Commit message (Expand) | Author | Age | Files | Lines | |
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* | [AMDGPU] gfx1010 VMEM and SMEM implementation | Stanislav Mekhanoshin | 2019-04-30 | 1 | -4/+4 |
* | [AMDGPU] Add MachineDCE pass after RenameIndependentSubregs | Stanislav Mekhanoshin | 2019-04-05 | 1 | -0/+4 |
* | [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmetic | Tim Renouf | 2019-03-18 | 1 | -4/+4 |
* | [AMDGPU] Shrinking V_SUBBREV_U32 | Stanislav Mekhanoshin | 2018-02-24 | 1 | -2/+2 |
* | Followup on Proposal to move MIR physical register namespace to '$' sigil. | Puyan Lotfi | 2018-01-31 | 1 | -12/+12 |
* | [AMDGPU] isRenamable fixes to support copy forwarding | Geoff Berry | 2018-01-30 | 1 | -4/+4 |
* | [MachineOperand][MIR] Add isRenamable to MachineOperand. | Geoff Berry | 2017-12-12 | 1 | -4/+4 |
* | AMDGPU: VALU carry-in and v_cndmask condition cannot be EXEC | Nicolai Haehnle | 2017-09-29 | 1 | -8/+8 |
* | [AMDGPU] Eliminate no effect instructions before s_endpgm | Stanislav Mekhanoshin | 2017-08-16 | 1 | -4/+0 |
* | [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32 | Stanislav Mekhanoshin | 2017-06-20 | 1 | -0/+101 |