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path: root/llvm/test/CodeGen/AMDGPU/shrink-carry.mir
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* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-4/+4
* [AMDGPU] Add MachineDCE pass after RenameIndependentSubregsStanislav Mekhanoshin2019-04-051-0/+4
* [AMDGPU] Asm/disasm clamp modifier on vop3 int arithmeticTim Renouf2019-03-181-4/+4
* [AMDGPU] Shrinking V_SUBBREV_U32Stanislav Mekhanoshin2018-02-241-2/+2
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-12/+12
* [AMDGPU] isRenamable fixes to support copy forwardingGeoff Berry2018-01-301-4/+4
* [MachineOperand][MIR] Add isRenamable to MachineOperand.Geoff Berry2017-12-121-4/+4
* AMDGPU: VALU carry-in and v_cndmask condition cannot be EXECNicolai Haehnle2017-09-291-8/+8
* [AMDGPU] Eliminate no effect instructions before s_endpgmStanislav Mekhanoshin2017-08-161-4/+0
* [AMDGPU] Fix illegal shrink of V_SUBB_U32 and V_ADDC_U32Stanislav Mekhanoshin2017-06-201-0/+101
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