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path: root/llvm/test/CodeGen/AMDGPU/salu-to-valu.ll
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* [DAGCombiner] [CodeGenPrepare] More comprehensive GEP splittingLuis Marques2019-06-171-12/+18
* AMDGPU: Select VOP3 form of addMatt Arsenault2019-05-081-1/+1
* [AMDGPU] Add MachineDCE pass after RenameIndependentSubregsStanislav Mekhanoshin2019-04-051-0/+1
* [AMDGPU] Change constant addr space to 4Yaxun Liu2018-02-131-55/+55
* [AMDGPU] Prevent post-RA scheduler from breaking memory clausesStanislav Mekhanoshin2017-09-191-2/+2
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-041-3/+3
* Revert r307026, "[AMDGPU] Switch scalarize global loads ON by default"NAKAMURA Takumi2017-07-041-3/+3
* [AMDGPU] Switch scalarize global loads ON by defaultAlexander Timofeev2017-07-031-3/+3
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-18/+18
* [AMDGPU] Remove getBidirectionalReasonRankStanislav Mekhanoshin2017-03-111-1/+1
* Codegen: Make chains from trellis-shaped CFGsKyle Butt2017-02-151-1/+1
* AMDGPU/SI: Don't move copies of immediates to the VALUTom Stellard2016-12-061-0/+25
* AMDGPU/SI: Fix visit order assumption in SIFixSGPRCopiesTom Stellard2016-11-111-0/+21
* AMDGPU/SI: Implement a custom MachineSchedStrategyTom Stellard2016-08-291-4/+2
* AMDGPU: Define priorities for register classesMatt Arsenault2016-05-211-2/+4
* AMDGPU/SI: Remove wait state handling for SMRD in SIInsertWaitsTom Stellard2016-04-301-1/+2
* [AMDGPU][llvm-mc] Support of Trap Handler registers (TTMP0..11 and TBA/TMA)gi...Artem Tamazov2016-04-131-16/+8
* AMDGPU/SI: Insert wait states required after v_readfirstlane on SITom Stellard2016-04-121-0/+1
* AMDGPU/SI: Use v_readfirstlane to legalize SMRD with VGPR base pointerTom Stellard2016-02-201-4/+8
* AMDGPU/SI: Detect uniform branches and emit s_cbranch instructionsTom Stellard2016-02-121-0/+28
* [AMDGPU] Assembler: Swap operands of flat_store instructions to match AMD ass...Tom Stellard2016-02-121-3/+3
* AMDGPU: Remove some old intrinsic uses from testsMatt Arsenault2016-02-111-17/+17
* AMDGPU/SI: Select non-uniform constant addrspace loads to flat instructions f...Tom Stellard2016-01-051-118/+151
* AMDGPU/SI: Select constant loads with non-uniform addresses to MUBUF instruct...Tom Stellard2015-12-151-37/+40
* AMDGPU: Split x8 and x16 vector loads instead of scalarizeMatt Arsenault2015-11-241-17/+10
* AMDGPU: Hack for VS_32 register pressureMatt Arsenault2015-11-061-9/+9
* AMDGPU: Fix splitting x16 SMRD loadsMatt Arsenault2015-09-281-0/+43
* AMDGPU: Fix moving SMRD loads with literal offsets on CIMatt Arsenault2015-09-281-1/+98
* AMDGPU: Add testcasesMatt Arsenault2015-09-281-0/+119
* AMDGPU: Cleanup testMatt Arsenault2015-09-281-82/+83
* AMDGPU: Assume SMRD access for constant address spaceMatt Arsenault2015-08-071-2/+30
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+118
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