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path: root/llvm/test/CodeGen/AMDGPU/regcoalesce-dbg.mir
Commit message (Expand)AuthorAgeFilesLines
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-021-1/+1
* [AMDGPU] gfx1010 VMEM and SMEM implementationStanislav Mekhanoshin2019-04-301-3/+3
* [AMDGPU] Add support for immediate operand for S_ENDPGMDavid Stuttard2019-03-121-1/+1
* MachineOperand/MIParser: Do not print debug-use flag, infer itMatthias Braun2018-10-301-1/+1
* AMDGPU: Fix tests using old number for constant address spaceMatt Arsenault2018-09-101-2/+2
* [DebugInfo] Add DILabel metadata and intrinsic llvm.dbg.label.Shiva Chen2018-05-091-1/+1
* Followup on Proposal to move MIR physical register namespace to '$' sigil.Puyan Lotfi2018-01-311-9/+9
* [CodeGen] Always use `printReg` to print registers in both MIR and debugFrancis Visoiu Mistrih2017-11-301-1/+1
* MIR: Print the register class or bank in vreg defsJustin Bogner2017-10-241-5/+5
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-1/+1
* [RegisterCoalescer] Do not call getInstructionIndex with DBG_VALUEBrendon Cahoon2017-02-041-0/+76
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