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path: root/llvm/test/CodeGen/AMDGPU/lshr.v2i16.ll
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* [SelectionDAG] ComputeKnownBits - minimum leading/trailing zero bits in LSHR/...Simon Pilgrim2020-01-131-22/+22
* (Re)generate various tests. NFCAmaury Sechet2019-10-081-57/+493
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-22/+8
* AMDGPU: Try a lot harder to emit scalar loadsMatt Arsenault2018-06-071-4/+12
* AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault2018-05-221-7/+16
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-171-1/+1
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-081-1/+1
* AMDGPU: Replace i64 add/sub loweringMatt Arsenault2017-11-151-1/+1
* [AMDGPU] Prevent post-RA scheduler from breaking memory clausesStanislav Mekhanoshin2017-09-191-3/+3
* AMDGPU: Start selecting global instructionsMatt Arsenault2017-07-291-11/+11
* AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)Konstantin Zhuravlyov2017-04-211-1/+1
* [AMDGPU] Resubmit SDWA peephole: enable by defaultSam Kolton2017-04-061-5/+4
* Revert r299536. [AMDGPU] SDWA peephole: enable by default.Ivan Krasin2017-04-051-4/+5
* [AMDGPU] SDWA peephole: enable by defaultSam Kolton2017-04-051-5/+4
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-8/+8
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-0/+150
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