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* AMDGPU/R600: Replace barrier intrinsicsMatt Arsenault2016-07-181-80/+0
| | | | llvm-svn: 275870
* MachineScheduler: Fully compare top/bottom candidatesMatthias Braun2016-06-251-1/+2
| | | | | | | | | | In bidirectional scheduling this gives more stable results than just comparing the "reason" fields of the top/bottom node because the reason field may be higher depending on what other nodes are in the queue. Differential Revision: http://reviews.llvm.org/D19401 llvm-svn: 273755
* AMDGPU: Define a schedule class for COPY.Matthias Braun2016-06-241-2/+1
| | | | | | | | | | COPY was lacking a scheduling class, define it to avoid regressions in the upcoming change to the bidirectional MachineScheduler. Approved by tstellar on IRC. Differential Revision: http://reviews.llvm.org/D21540 llvm-svn: 273751
* AMDGPU: Run pointer optimization passesMatt Arsenault2016-06-151-9/+28
| | | | llvm-svn: 272736
* AMDGPU/SI: Enable load-store-opt by default.Changpeng Fang2016-05-261-3/+1
| | | | | | | | | | Summary: Enable load-store-opt by default, and update LIT tests. Reviewers: arsenm Differential Revision: http://reviews.llvm.org/D20694 llvm-svn: 270894
* AMDGPU/SI: Improve MachineSchedModel definitionTom Stellard2016-03-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch contains a few improvements to the model, including: - Using a single resource with a defined buffers size for each memory unit. - Setting the IssueWidth correctly. - Fixing latency values for memory instructions. shader-db stats: 16429 shaders in 3231 tests Totals: SGPRS: 318232 -> 312328 (-1.86 %) VGPRS: 208996 -> 209346 (0.17 %) Code Size: 7147044 -> 7166440 (0.27 %) bytes LDS: 83 -> 83 (0.00 %) blocks Scratch: 1862656 -> 1459200 (-21.66 %) bytes per wave Max Waves: 49182 -> 49243 (0.12 %) Wait states: 0 -> 0 (0.00 %)A Differential Revision: http://reviews.llvm.org/D18453 llvm-svn: 264877
* AMDGPU: Rework how private buffer passed for HSAMatt Arsenault2015-11-301-1/+1
| | | | | | | | | | | | | | | | If we know we have stack objects, we reserve the registers that the private buffer resource and wave offset are passed and use them directly. If not, reserve the last 5 SGPRs just in case we need to spill. After register allocation, try to pick the next available registers instead of the last SGPRs, and then insert copies from the inputs to the reserved registers in the progloue. This also only selectively enables all of the input registers which are really required instead of always enabling them. llvm-svn: 254331
* AMDGPU: Add sdst operand to VOP2b instructionsMatt Arsenault2015-08-291-1/+1
| | | | | | | | | | The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. llvm-svn: 246358
* Fix "the the" in comments.Eric Christopher2015-06-191-1/+1
| | | | llvm-svn: 240112
* R600 -> AMDGPU renameTom Stellard2015-06-131-0/+63
llvm-svn: 239657
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