| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | AMDGPU: Rework how private buffer passed for HSA | Matt Arsenault | 2015-11-30 | 1 | -1/+1 | 
| | | | | | | | | | | | | | | | | | If we know we have stack objects, we reserve the registers that the private buffer resource and wave offset are passed and use them directly. If not, reserve the last 5 SGPRs just in case we need to spill. After register allocation, try to pick the next available registers instead of the last SGPRs, and then insert copies from the inputs to the reserved registers in the progloue. This also only selectively enables all of the input registers which are really required instead of always enabling them. llvm-svn: 254331 | ||||
| * | AMDGPU: Add sdst operand to VOP2b instructions | Matt Arsenault | 2015-08-29 | 1 | -1/+1 | 
| | | | | | | | | | | | The VOP3 encoding of these allows any SGPR pair for the i1 output, but this was forced before to always use vcc. This doesn't yet try to use this, but does add the operand to the definitions so the main change is adding vcc to the output of the VOP2 encoding. llvm-svn: 246358 | ||||
| * | Fix "the the" in comments. | Eric Christopher | 2015-06-19 | 1 | -1/+1 | 
| | | | | | llvm-svn: 240112 | ||||
| * | R600 -> AMDGPU rename | Tom Stellard | 2015-06-13 | 1 | -0/+63 | 
| llvm-svn: 239657 | |||||

