Commit message (Expand) | Author | Age | Files | Lines | |
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* | [AMDGPU] Support mov dpp with 64 bit operands | Stanislav Mekhanoshin | 2019-10-15 | 1 | -6/+59 |
* | [AMDGPU] gfx1010 dpp16 and dpp8 | Stanislav Mekhanoshin | 2019-06-12 | 1 | -16/+27 |
* | AMDGPU: Select VOP3 form of add | Matt Arsenault | 2019-05-08 | 1 | -1/+2 |
* | AMDGPU: Add support for cross address space synchronization scopes | Konstantin Zhuravlyov | 2019-03-25 | 1 | -2/+2 |
* | [AMDGPU]: Turn on the DPP combiner by default | Valery Pykhtin | 2018-12-05 | 1 | -2/+2 |
* | Relax fast register allocator related test cases; NFC | Matthias Braun | 2018-10-29 | 1 | -1/+1 |
* | [AMDGPU] Divergence driven instruction selection. Part 1. | Alexander Timofeev | 2018-09-21 | 1 | -2/+1 |
* | run post-RA hazard recognizer pass late | Mark Searles | 2018-07-16 | 1 | -1/+30 |
* | [AMDGPU] Add llvm.amdgpu.update.dpp intrinsic | Connor Abbott | 2017-08-08 | 1 | -0/+17 |