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path: root/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
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* [DAGCombine] GetNegatedExpression - constant float vector support (PR42105)Simon Pilgrim2019-06-111-9/+8
* AMDGPU: Add pass to lower kernel arguments to loadsMatt Arsenault2018-06-261-2/+3
* AMDGPU: Use scalar operations for f16 fabs/fneg patternsMatt Arsenault2018-06-071-19/+8
* AMDGPU: Try a lot harder to emit scalar loadsMatt Arsenault2018-06-071-7/+7
* AMDGPU: Custom lower v2f16 fneg/fabs with illegal f16Matt Arsenault2018-06-061-2/+4
* AMDGPU: Use better alignment for kernarg loweringMatt Arsenault2018-05-301-11/+5
* AMDGPU: Fix v2f16 fneg/fabs patternMatt Arsenault2018-05-221-2/+20
* AMDGPU: Make v2i16/v2f16 legal on VIMatt Arsenault2018-05-221-14/+10
* [AMDGPU] Enabled v2.16 literals for VOP3PStanislav Mekhanoshin2018-04-171-3/+3
* AMDGPU/GCN: Bring processors in sync with AMDGPUUsageKonstantin Zhuravlyov2017-12-081-1/+1
* [DAGCombine] (shl (or x, c1), c2) -> (or (shl x, c2), c1 << c2)Simon Pilgrim2017-09-141-14/+13
* [AMDGPU] Added extra test checks to make D19325 diff clearerSimon Pilgrim2017-09-051-5/+11
* AMDGPU: Start selecting global instructionsMatt Arsenault2017-07-291-2/+2
* AMDGPU: Allow SIShrinkInstructions to work in non-SSAMatt Arsenault2017-07-101-2/+2
* [AMDGPU] Untangle SDWA pass from SIShrinkInstructionsStanislav Mekhanoshin2017-06-031-4/+4
* [AMDGPU] Allow SDWA in instructions with immediates and SGPRsStanislav Mekhanoshin2017-05-301-5/+12
* AMDGPU: Temporarily disable packed inlinable literals (v2f16, v2i16)Konstantin Zhuravlyov2017-04-211-1/+1
* AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernelMatt Arsenault2017-03-211-10/+10
* AMDGPU: Support v2i16/v2f16 packed operationsMatt Arsenault2017-02-271-32/+85
* AMDGPU : Add trap handler support.Wei Ding2017-02-101-2/+2
* AMDGPU: Use source modifiers with f16->f32 conversionsMatt Arsenault2017-02-021-33/+20
* AMDGPU: Fix f16 fabs/fnegMatt Arsenault2016-11-151-0/+113
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