summaryrefslogtreecommitdiffstats
path: root/llvm/test/CodeGen/AMDGPU/extract_subvector_vec4_vec3.ll
Commit message (Expand)AuthorAgeFilesLines
* Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders2020-01-081-2/+2
* Revert "[MIR] Target specific MIR formating and parsing"Nico Weber2020-01-081-2/+2
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-2/+2
* Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders2020-01-081-2/+2
* [MIR] Target specific MIR formating and parsingPeng Guo2020-01-081-2/+2
* AMDGPU: Relax 32-bit SGPR register classMatt Arsenault2019-10-181-4/+3
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-141-3/+3
* AMDGPU: Use SGPR_128 instead of SReg_128 for vregsMatt Arsenault2019-10-101-2/+2
* [AMDGPU] Extend buffer intrinsics with swizzlingPiotr Sobczak2019-10-021-2/+2
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-3/+3
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-3/+3
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-3/+3
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-3/+3
* [CodeGen] Fixed de-optimization of legalize subvector extractTim Renouf2019-05-161-0/+37
OpenPOWER on IntegriCloud