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path: root/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
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* Revert "[AMDGPU] Invert the handling of skip insertion."Nicolai Hähnle2020-02-031-4/+7
* [AMDGPU] Invert the handling of skip insertion.cdevadas2020-01-151-7/+4
* [AMDGPU] Fix emitIfBreak CF lowering: use temp reg to make register coalescer...vpykhtin2019-11-261-13/+13
* [AMDGPU] Come back patch for the 'Assign register class for cross block value...Alexander Timofeev2019-10-141-17/+15
* Revert [MBP] Disable aggressive loop rotate in plain modeJordan Rupprecht2019-08-291-22/+26
* [MBP] Disable aggressive loop rotate in plain modeGuozhi Wei2019-08-221-26/+22
* Revert r368339 "[MBP] Disable aggressive loop rotate in plain mode"Hans Wennborg2019-08-121-22/+26
* [MBP] Disable aggressive loop rotate in plain modeGuozhi Wei2019-08-081-26/+22
* [AMDGPU] LCSSA pass added in preISel. Uniform values defined in the divergent...Alexander Timofeev2019-07-021-22/+25
* [MBP] Move a latch block with conditional exit and multi predecessors to top ...Guozhi Wei2019-06-141-20/+21
* [AMDGPU] Partial revert for the ba447bae7448435c9986eece0811da1423972fddAlexander Timofeev2019-06-061-25/+30
* [AMDGPU] Divergence driven ISel. Assign register class for cross block va...Alexander Timofeev2019-05-261-30/+25
* Revert r361644, "[AMDGPU] Divergence driven ISel. Assign register class for c...Peter Collingbourne2019-05-251-25/+30
* [AMDGPU] Divergence driven ISel. Assign register class for cross block values...Alexander Timofeev2019-05-241-30/+25
* AMDGPU: test for uniformity of branch instruction, not its conditionRhys Perry2019-01-071-0/+97
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