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path: root/llvm/test/CodeGen/AMDGPU/callee-frame-setup.ll
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* [AMDGPU] Created a sub-register class for the return address operand in the r...Christudasan Devadasan2019-07-091-24/+31
* AMDGPU: Make s34 the FP registerMatt Arsenault2019-07-081-41/+304
* AMDGPU: Always use s33 for global scratch wave offsetMatt Arsenault2019-06-201-11/+13
* AMDGPU: Fix ignoring DisableFramePointerElim in leaf functionsMatt Arsenault2019-06-201-4/+41
* AMDGPU: Don't fix emergency stack slot at offset 0Matt Arsenault2019-06-051-8/+8
* AMDGPU: Invert frame index offset interpretationMatt Arsenault2019-06-051-4/+3
* AMDGPU: Don't enable all lanes with non-CSR VGPR spillsMatt Arsenault2019-05-281-0/+16
* AMDGPU: Activate all lanes when spilling CSR VGPR for SGPR spillsMatt Arsenault2019-05-241-7/+19
* AMDGPU: Increase default stack alignmentMatt Arsenault2018-03-291-2/+2
* AMDGPU: Fix not preserving CSR VGPR if used for SGPR spillsMatt Arsenault2018-03-271-0/+31
* [AMDGPU] added writelane intrinsicTim Renouf2018-02-281-1/+1
* [AMDGPU] Switch to the new addr space mapping by defaultYaxun Liu2018-02-021-4/+4
* [CodeGen] Unify MBB reference format in both MIR and debug outputFrancis Visoiu Mistrih2017-12-041-4/+4
* AMDGPU: Remove error on calls for amdgcnMatt Arsenault2017-08-031-2/+2
* AMDGPU: Fix clobbering CSR VGPRs when spilling SGPR to itMatt Arsenault2017-08-021-5/+18
* AMDGPU: Initial implementation of callsMatt Arsenault2017-08-011-1/+57
* AMDGPU: Setup SP/FP in callee function prolog/epilogMatt Arsenault2017-06-261-0/+27
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